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2801 筆查詢結果
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
Digital circuit design for DTCO(Design technology Co-Optimization)
4天以前更新 兩週內0-5人應徵
2022-01-18
智成電子股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.In charge of digital circuit design/verify by Verilog/VHDL 2.Familiar with ASIC design flow or FPGA development is a plus. 3.Familiar with MCU SoC design is a plus. 4.Familiar with RF baseband design is a plus.
一個月以前更新 兩週內0-5人應徵
2021-12-01
Marvell_邁威爾科技有限公司
  • 碩士
  • 八年以上工作經驗
  • 待遇面議
The Opportunity Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. Job Responsibilities: This position is to build and lead a digital design team for the Analog & Mixed-Signal IP development in Marvell Central Engineering. The responsibilities include but not limited to. * Build and manage a strong digital
4天以前更新 兩週內0-5人應徵
2022-01-18

Sr./Staff Digital IC Design Engineer

FULL_TIME
新竹縣竹北市
萬典科技股份有限公司
  • 大學 碩士
  • 一年以上工作經驗
  • 待遇面議
1. HDL coding and design verification for TDDI products 2. System validation/debug and customer issues support 3. CP test pattern generation and co-work with test engineer for CP testing 4. Area/power optimization, and design trade-off analysis 5. Lint/ CDC analysis for digital design 6. Schedule tasks and goals to complete designs on time that meet all specifications
3天以前更新 兩週內0-5人應徵
2022-01-19

Sr. Staff Digital Design Engineer_2102841

FULL_TIME
新竹縣竹北市
Marvell_邁威爾科技有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
The Opportunity Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. Job Responsibilities: Job Responsibilities: ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in engineering implementation
4天以前更新 兩週內0-5人應徵
2022-01-18
佳易科技股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
As senior/staff digital design engineer, this person is required to support all digital design activities on company products, design services as well as internal IP development. Below are the responsibilities: - Responsible for RTL Design and writing of test bench - experience in IP core design such as peripheral interfaces, CPU cores, digital controllers - Architecture review, RTL design, fun
4天以前更新 兩週內0-5人應徵
2022-01-18

Digital ASIC Design Engineer

FULL_TIME
新竹市
瑞典商_芬格科技有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
To strengthen and building up our new ASIC team in Hsinchu, Taiwan, we are looking for Digital ASIC Design Engineers who wants to make a difference and strengthen the development of Fingerprint’s sensor technology. You will report directly to the ASIC Manager/Project Manager in Hsinchu. We offer you an exciting and challenging position together with friendly and professional colleagues. Work in a
5天以前更新 兩週內0-5人應徵
2022-01-17
創鑫智慧股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Neuchips is looking for a senior digital IC designer for IC design flow who can contribute organizationally of our AI solution to the world. Responsibilities: - EDA tools and design flow build-up Qualifications/Skills: - Familiarity with RTL coding - Familiarity with scripting (such as Pearl and TCL language) - Understanding of timing constraint (SDC) - Experience in IC design flow such as simu
3天以前更新 兩週內0-5人應徵
2022-01-19

Sensor Digital Circuit Design Engineer

FULL_TIME
新竹縣竹北市
光程研創股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
Artilux are looking for an outstanding engineer who are as excited to bring new architectures for advanced Ics, with high quality and exceptional performance. • Circuit design for general sensors-Digital
5天以前更新 兩週內0-5人應徵
2022-01-17

Senior Analog Hardware Design Engineer

FULL_TIME
新竹縣竹北市
美商艾科斯羅國際股份有限公司台灣分公司
  • 大學以上
  • 五年以上工作經驗
  • 月薪 40,000 元以上
Job Summary: This position is for a senior hardware design engineer reporting into the Digital/Mixed Signal product development group. The successful candidate will be leading the development of high-performance analog/mixed signal technology as a member of our product development team for PCB instrumentation in many design areas, including: 1. Precision measurement 2. Signal sourcing, and DSP
5天以前更新 兩週內0-5人應徵
2022-01-17
科締納科技股份有限公司_Cortina Systems Taiwan Limited
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
Senior level ASIC design engineer [Responsibility] Module level design and verification activities including: • Design digital control or datapath logic using Verilog HDL • Design synthesis using RTL Complier • RTL linting using preferred lint tool SoC integration FPGA design and lab debug
一週以前更新 兩週內0-5人應徵
2022-01-14
Marvell_邁威爾科技有限公司
  • 碩士
  • 八年以上工作經驗
  • 待遇面議
The Opportunity Central Engineering AMS-IP team provides leading-edge SerDes PHY solutions and other Analog Mixed-Signal IPs to support all Marvell products. This position is to build and lead a digital design verification team for the Analog & Mixed-Signal IP development in Marvell Central Engineering. The responsibilities include but not limited to. * Build and manage a strong digital design v
4天以前更新 兩週內0-5人應徵
2022-01-18
創鑫智慧股份有限公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
Neuchips is looking for a senior digital IC designer for design verification who can contribute organizationally of our AI solution to the world. Responsibilities: - Verify AMBA bus fabric using VIP - Verify in-house AI accelerator design Qualifications/Skills: - Familiarity with SystemVerilog and UVM - Familiarity with AMBA protocol - Experience in VIP usage Education and experiment requireme
4天以前更新 兩週內0-5人應徵
2022-01-18
NVIDIA_英屬維京群島商輝達維京股份有限公司台灣分公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
We're looking for a Senior Digital Design Verification Engineer. As a Senior Mixed Signal Digital Design Verification engineer at NVIDIA, you'll verify the design and implementation of our cutting edge SerDes IPs. This ground breaking technology will enable and accelerate gaming, artificial intelligence, deep learning, and autonomous driving. We have put together a world-class team that deliver
一週以前更新 兩週內0-5人應徵
2022-01-12
Qualcomm Semiconductor Corporation_高通半導體有限公司
  • 大學以上
  • 五年以上工作經驗
  • 待遇面議
QCTs CPU Subsystem Team in Taiwan is actively seeking engineers for the CPU Subsystem Physical Design Team. As a physical design engineer you will innovate, develop, and implement CPU cores using state-of-the-art tools and technologies. This is an excellent opportunity to be part of a fast paced team responsible for delivering Snapdragon CPU design implementations for high performance SoCs in sub-
1天以前更新 兩週內0-5人應徵
2022-01-21
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