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3211 筆查詢結果

APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 3.Requirement: 3-1. Familiar with ASIC design flow相關尤佳 3-2. Hands on APR physical design from netlist to DRC/LVS tapeout experience is required 3-3. Familiar with hierarchical and/or low power design flow相關尤佳
一週以前更新 兩週內11-30人應徵
2021-11-15

Physical Design Engineer APR

FULL_TIME
新竹市
104獵才顧問_一零四資訊科技股份有限公司
  • 大學以上
  • 三年以上工作經驗
  • 待遇面議
1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis.
一週以前更新 兩週內0-5人應徵
2021-11-21

Physical Design Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. APR Implementation. - floorplan, placement, clock tree synthesis - routing, timing optimization. 2. Physical verification. (DRC/LVS) 3. Timing Closure. - STA - PT, Tweaker 4. Power analysis and fixing (IR/EM). 5. Low power implementation. - UPF flow
三週以前更新 兩週內0-5人應徵
2021-11-02

Physical Design Engineer

FULL_TIME
新竹市
益芯科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Must have BS in EE/CE/CS of relevant experience in IC design field. 2. Familiar with IC design flow : *Chip integration and floorplan *APR physical design *Fully customized layout *DRC/LVS to tapeout 3. Engineering discipline, passion, and willing to teamwork. 4. Circuit knowledge and analog/logic design relevant experience would be a plus.
4天以前更新 兩週內0-5人應徵
2021-11-24

資深APR Physical Design Engineer

FULL_TIME
新竹縣竹北市
聯詠科技股份有限公司
  • 碩士以上
  • 四年以上工作經驗
  • 待遇面議
1.Physical design of multi-million instance-count SOC project. Physical design activities include floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc. (APR Support) 2.Build advanced physical design methodology to facilitate UDSM design project for timing/power/DFM closure and CPU/GPU hardening. 3.Requirement: 3-1. Familiar with Cadence EDI Platform and/or Syno
一週以前更新 兩週內0-5人應徵
2021-11-15

Physical Design Engineer

FULL_TIME
新竹市
翊傑科技股份有限公司
  • 大學 碩士
  • 五年以上工作經驗
  • 待遇面議
職務說明 1. Location:新竹 2. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 3. Support STA timing analysis and fixing 4. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. 5. Perform power analysis / IR drop analysis ※Requirements: 1. Familiar with Cadence EDI or other auto place and route t
2天以前更新 兩週內0-5人應徵
2021-11-26
原相科技股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
1.IC Implementation & Verification - including floorplan, CTS, STA, IR-drop analysis, DRC&LVS. 2.Familiar with EDA tools including ICC , Encounter 3.TCL/perl script programming. 4.Low power flow is preferred.
5天以前更新 兩週內6-10人應徵
2021-11-23
聯發科技股份有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1.SoC Chip Top and Infrastructure integration and physical design 2.Participate in SoC design implementation from logic synthesis to physical implementation stage under the latest technology process
4天以前更新 兩週內0-5人應徵
2021-11-24
創意電子股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Develop 2.5D/3D-IC multi-die stacking design flow for TSMC CoWoS, InFO, SoIC advanced technology 2. Deploy and enhance 2.5D/3D-IC physical design flow in real design with performing 3D multi-die stacking tasks: die-stacking configuration, floorplanning, layout, and die-to-die auto-routing 3. Develop 2.5D/3D-IC extraction signoff flow to ensure signal and power integrity 4. Design
6天以前更新 兩週內6-10人應徵
2021-11-22
聯陽半導體股份有限公司
  • 碩士
  • 工作經驗不拘
  • 待遇面議
1. APR Implementation Flow (For Astro/ICC/StarRC Tools). 2. STA Timing Analysis Flow (For PrimeTime Family Tools).
6天以前更新 兩週內0-5人應徵
2021-11-22
聯陽半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
1. APR Implementation Flow (For Astro/ICC/ICCII/StarRC Tools). 2. STA Timing Analysis Flow (For PrimeTime Family Tools).
6天以前更新 兩週內0-5人應徵
2021-11-22
智原科技股份有限公司
  • 大學 碩士
  • 工作經驗不拘
  • 待遇面議
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.
一週以前更新 兩週內11-30人應徵
2021-11-15
NVIDIA_英屬維京群島商輝達維京股份有限公司台灣分公司
  • 碩士以上
  • 三年以上工作經驗
  • 待遇面議
We are now looking for a Senior Physical Design Engineer in Taiwan, Hsinchu office. What you will be doing: A senior role in physical design for NVIDIA GPU and Mobile chips. Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verificat
兩週以前更新 兩週內6-10人應徵
2021-11-11
台灣愛渠西來技術股份有限公司
  • 大學以上
  • 四年以上工作經驗
  • 年薪 1,200,000 元以上
需要英文視訊面試 · Must have 4+ years of relevant experience with exposure to 10nm or lower nodes. · Ability to independently handle complex blocks to closure right from Synthesis, Worked on at least 2 end to end projects those spanned across entire life cycle of development, Ability to communicate with architecture, RTL design and other remote teams · Performing a wide range of back-end activitie
5天以前更新 兩週內0-5人應徵
2021-11-23
台灣愛渠西來技術股份有限公司
  • 大學以上
  • 四年以上工作經驗
  • 年薪 1,200,000 元以上
需要英文視訊面試 · Must have 4+ years of relevant experience with exposure to 10nm or lower nodes. · Ability to independently handle complex blocks to closure right from Synthesis, Worked on at least 2 end to end projects those spanned across entire life cycle of development, Ability to communicate with architecture, RTL design and other remote teams · Performing a wide range of back-end activitie
5天以前更新 兩週內0-5人應徵
2021-11-23
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