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CAD Engineer

FULL_TIME
新竹市
智成電子股份有限公司
  • 大學以上
  • 二年以上工作經驗
  • 待遇面議
1. Front-end IC design flow development/maintain/support 2. Standard cell library design & modeling & maintain 3. IC tape out project support
1天以前更新 兩週內0-5人應徵
2021-12-01

CAD Engineer/Manager

FULL_TIME
新竹市
晶豪科技股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
1. Tools automation script. 2. LVS and DRC rule maintenance. 3. Standard cell/ model/… Design & Layout library maintenance. 4. CAD tool evaluation, usage, maintenance & contact with EDA vendor. 5. EDA license maintain. 6. Provide training, documentation & user support. 7. 熟悉Synopsys, Cadence, mentor EDA 軟體.
6天以前更新 兩週內0-5人應徵
2021-11-26

CAD Engineer

FULL_TIME
新竹縣竹北市
萬有半導體有限公司
  • 大學
  • 三年以上工作經驗
  • 待遇面議
CAD Projects - Adding and improving grid/Isf tools (Linux) - Automation of project setup and user adding (Linux) - CAD tool license usage monitors (Linux) - Noisy Sensitive Tools (Front End, Back End) - Simulation batch run tools (Front End) CAD Ongoing Tasks: - Creating and archiving projects (Linux) - Adding Users to projects (Linux) - Setting up Jira users and projects (Application) - Setting
2天以前更新 兩週內0-5人應徵
2021-11-30

Cell Library CAD engineer

FULL_TIME
新竹市
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
As an Cell Library CAD engineer, you will be in charge of one of following job functions: 1. Standard cell library characterization flow development 2. Standard cell library front-end model generation and verification flow development 3. IP backend model generation and QA flow development and maintaining 4. IP behavior model creation and maintaining
3天以前更新 兩週內0-5人應徵
2021-11-29

Standard Cell CAD Engineer

FULL_TIME
新竹市
台灣積體電路製造股份有限公司(台積電)
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址:https://bit.ly/3pacoi0 Description 1.Play a strategic role of applying AI/machine-learning techniques to your (and colleagues’) daily work, including circuit design analysis, characterization, QA, and silicon debug. 2.Be the expert of library design kit and lead TSMC-EDA-IC design cooperation. 3.Provide end-
兩個月以前更新 兩週內0-5人應徵
2021-09-13

CAD Engineer

FULL_TIME
新竹市
瓦雷科技有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.
6天以前更新 兩週內0-5人應徵
2021-11-26

Staff CAD Engineer

FULL_TIME
新竹市
台灣英飛朗股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 年薪 1,500,000 ~ 3,000,000 元
Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of t
1天以前更新 兩週內0-5人應徵
2021-12-01

數字IP工程师/ Digital CAD Engineer

FULL_TIME
新竹縣竹北市
台灣矽力杰科技股份有限公司
  • 碩士以上
  • 五年以上工作經驗
  • 待遇面議
提供數字/混模電路設計的CAD 支持,負責公司内部數字IP 模塊的開發和外部IP Vendor 的技術聯絡。 Digital CAD Engineer, working as part of the CAD team on development and support of digital and mixed signal design flows, driving the in-house development of digital IP building block, and acting as the primary technical liaison between the company and external IP vendors
一週以前更新 兩週內0-5人應徵
2021-11-23

Analog CAD Engineer

FULL_TIME
新竹縣竹北市
M31 Technology Corporation_円星科技股份有限公司
  • 碩士以上
  • 二年以上工作經驗
  • 待遇面議
1. Maintenance and flow improvement of Physical Verification 2. XRC/StarRC/QRC flow development and execution efficiency and accuracy analysis 3. PERC Calibre PERC programming 4. DRC/LVS/LPE for multiple GDS can be automatically processed by script 5. Automated programming : Layout -> DRC/LVS -> PERC -> LPE 6. Use calibre DRC and calibre designrev to automatically generate layout
1天以前更新 兩週內0-5人應徵
2021-12-01
智原科技股份有限公司
  • 大學以上
  • 工作經驗不拘
  • 待遇面議
1. Foundry & In-house DRC/LVS/LPE/PERC rule deck maintain & creation 2. Physical verification CAD flow establishment & maintenance 3. Issue solving for ASIC project & IP development DRC/LVS problem
兩週以前更新 兩週內0-5人應徵
2021-11-15

DFT CAD Engineer

FULL_TIME
新竹縣竹北市
擎亞台灣半導體股份有限公司
  • 碩士
  • 三年以上工作經驗
  • 待遇面議
(1) DFT design methodology development. (2) Flow development for MBIST, SCAN & ATPG. (3) In-house DFT design-kit/utility/script development.
一個月以前更新 兩週內0-5人應徵
2021-11-02

Analog CAD Engineer

FULL_TIME
新竹市
創意電子股份有限公司
  • 大學 碩士
  • 三年以上工作經驗
  • 待遇面議
※Job Contents: 1. IP design flow development 2. In-house utility development for IP design 3. EDA tool evaluation, usage, maintenance, Q&A window with tool vendor 4. 具備programming 能力 ( C/C++, TCL script, C-shell 或perl 其中一項以上 ) 5. Familiar with Virtuoso SKILL writing, Calibre rule writing, or other EDA tools is a plus. ※Requirements: 1. 熟 Verilog language, Verilog simulator 2. 有IP beh
3天以前更新 兩週內0-5人應徵
2021-11-29
智原科技股份有限公司
  • 大學以上
  • 一年以上工作經驗
  • 待遇面議
1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design
兩週以前更新 兩週內0-5人應徵
2021-11-15

數位IC設計工程師 (CAD engineer)

FULL_TIME
新竹縣竹北市
DIGWISE_崛智科技有限公司
  • 碩士
  • 二年以上工作經驗
  • 待遇面議
1) Build up IP behavior model. 2) Memory compiler development. 3) Standard cell library re-k; cell analyze, debug, and PPA. 4) Support company design flow related script; script writing, utility programming.
一週以前更新 兩週內0-5人應徵
2021-11-25

Standard Cell Library Engineer

FULL_TIME
新竹縣竹北市
松翰科技股份有限公司
  • 大學 碩士
  • 二年以上工作經驗
  • 待遇面議
1. Analog-IP liberty characterization and creation 2. Re-K Standard cell liberty 3. Verilog behavior model 4. Siliconsmart characterization flow/script establishment and maintenance 5. Run HSPICE & Verilog Simulation to confirm the correctness of the .lib/.v model
1天以前更新 兩週內0-5人應徵
2021-12-01
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