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智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: 1. Study / research / develop DFT design flow 2. Maintain inhouse DFT utilities. 職務條件: 1. 碩士以上,電子、電機、資訊工程相關系所畢業 2. 熟悉 DFT概念及EDA Tool者為佳 3. 熟悉 C/C++ or Tcl ※請同學附上履歷自傳、論文摘要/研究作品以及成績單。
一個月以前更新 兩週內0-5人應徵
2021-12-03
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: Responsible for the development and implementation for advanced at speed testing and other DFT, JTAG, memory bist, scan chain and ATPG, for ASIC projects. 職務條件: 1. 碩士以上,電子、電機、資訊工程相關系所畢業 2. 熟悉 DFT概念及EDA Tool者為佳 3. 熟悉 Logic Design or Verilog Language ※請同學附上履歷自傳、論文摘要/研究作品以及成績單。
一個月以前更新 兩週內0-5人應徵
2021-12-03
安霸股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
1. Digital IP development and design spec/architecture documentation. 2. SoC system bus design. 3. SoC integration and design quality verification. 4. Mass production pattern development and debug. 5. IC development flow enhancement. 6. Team work for advanced SoC development.
4天以前更新 兩週內0-5人應徵
2022-01-20
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: 1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint va
一個月以前更新 兩週內0-5人應徵
2021-12-03
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
Front-End EDA Engineer ※Job Contents: 1. Responsible for IC front-end design methodology development and project support. 2. Flow development for lint, constraint check, synthesis, STA, power analysis and so on. 3. In house EDA utility development ※Requirements: 1. MS in Electronic engineer or Computer science 2. Experience in R2N flow development (lint/constraint check/synthesis/STA/Simulation/f
3小時以前更新 兩週內0-5人應徵
2022-01-24
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
-Master Degree or above, Solid background in C and C++ -Familiar with embedded system, computer architecture, operating system -Experience in Linux Kernel Driver (Display part preferred), Android System Infrastructure, Windows Driver.
4天以前更新 兩週內0-5人應徵
2022-01-20
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
-Solid integrated circuit and solid state devices knowledge -Familiar with circuit design EDA tools -Knowledges in the following areas are a plus:  PLL, high speed circuit design, I/O design, LVDS, ESD, ADC/DAC, switching regulator, low noise design
4天以前更新 兩週內0-5人應徵
2022-01-20
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
-Master/PhD Degree in EE/CS or relevant -Solid knowledge of semiconductor logic design and flow. -Good understanding of video, computer and communications systems is a plus -It is a plus to be familiar with DisplayPort, HDMI, USB and PC Express or other communication protocols
4天以前更新 兩週內0-5人應徵
2022-01-20
英屬蓋曼群島商譜瑞科技股份有限公司台灣分公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
-Master/PhD Degree, in EE/CS or relevant - embedded microcontroller, embedded control application background -Solid“C”and assembly language familiarity - Knowledgeable on analog and MCU based application design
4天以前更新 兩週內0-5人應徵
2022-01-20
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: 1. Support Serdes IP R&D to solve all system issues 2. Support Serdes IP customers to solve all system application issues. 職務條件: 1. Master or PHD degree, EE/ communication / Biomedical engineering or related department 2. Familiar with Verilog RTL, simulation, synthesis, STA. 3. Has attended “signal and system” course. 4. Has FPGA experience is a plus. ※請同學附上履歷自傳、論文摘
一個月以前更新 兩週內0-5人應徵
2021-12-03
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: Responsible for ASIC/SoC physical design (P&R) and physical verification. 職務條件: 1. 碩士以上,電子、電機、資訊工程相關系所畢業 2. 熟悉 CMOS 設計原理 3. 操作過 APR tool ( Innovus or ICC) 者為佳 4. 熟悉 TCL, C or Shell Language ※請同學附上履歷自傳、論文摘要/研究作品以及成績單。
一個月以前更新 兩週內0-5人應徵
2021-12-03
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: 1. APR flow development. 2. Develop methodology and construct flow for timing closure and clock tree quality. 3. CAD tool evaluation and consultant for physical design. 職務條件: 1. 碩士以上,電子、電機、資訊工程相關系所畢業 2. 熟悉 C or Tcl or Perl 3. 操作過 APR tool ( Innovus or ICC) 者為佳 ※請同學附上履歷自傳、論文摘要/研究作品以及成績單。
一個月以前更新 兩週內0-5人應徵
2021-12-03
智原科技股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
職務內容: 1. Front-end design flow development 2. Logic Synthesis, STA, LEC, ECO flow creation and consultant 職務條件: 1. 碩士以上,電子、電機、資訊工程相關系所畢業 2. Familiar with script language (ex.,C/C++, TCL, Perl) 3. Experience of use SoC design timing analysis, logic synthesis is a plus ※請同學附上履歷自傳、論文摘要/研究作品以及成績單。
一個月以前更新 兩週內0-5人應徵
2021-12-03
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1.Took responsibility of creating SDC for the complex SoC. 2.Took responsibility of timing analysis with customer. 3.Took responsibility of planning low-power structure and review flow (CPF/UPF) 4.Supported back-end team in post-layout timing closures 5.Supported project team in central tech-library management 6.Run EDA-Tool and GUC in-house design kit. ※Requirements: 1.Familiar wi
3小時以前更新 兩週內0-5人應徵
2022-01-24
創意電子股份有限公司
  • 碩士以上
  • 工作經驗不拘
  • 待遇面議
※Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. ※請同學附上論文/研
3小時以前更新 兩週內0-5人應徵
2022-01-24
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