【本職缺僅接受台積電官方網站投遞】 請至台積電官方網站投遞個人履歷表,此職缺履歷登錄網址: https://careers.tsmc.com/careers/JobDetail?jobId=545&source=104 Established in 1987 and headquartered in Taiwan, TSMC pioneered the pure-play foundry business model with an exclusive focus on manufacturing its customers’ products. In 2023, the company served 528 customers with 11,895 products for high performance computing, smartphones, IoT, automotive, and consumer electronics, and is the world’s largest provider of logic ICs with annual capacity of 16 million 12-inch equivalent wafers. TSMC operates fabs in Taiwan as well as manufacturing subsidiaries in Washington State, Japan and China, and its ESMC subsidiary plans to begin construction on a fab in Germany in 2024. In Arizona, TSMC is building three fabs, with the first starting 4nm production in 2025, the second by 2028, and the third by the end of the decade. Responsibilities: 1.Hands on SOC chip/ block implementation from gate level netlist to GDS tape-out. 2.Develop IC design methodology 3.Chip tape-out; Design methodology development
待遇面議
(經常性薪資達 4 萬元或以上)
1.Experience in tape-out with multi-million gates count SOC design. 16nm/10nm/7nm design experience is a plus. 2.Solid skillsets of Cadence/Synsopsys/Mentor EDA tools. 3.Capable of executing timing budgeting, synthesis, P&R, CTS, timing closure, DFT, physical verification, DFM and spice simulations. 4.Experience in CAD methodology and problem solving skill. 5.Familiar with Verilog, Perl/Tcl and C/C++. 6.Good communication in English 7.Master Degree or above
詳見企業網站 http://www.tsmc.com/chinese/careers/compensation_benefits.htm 如欲投遞履歷,請上台積官網 http://www.tsmc.com/chinese/careers/index.htm