1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance
2.Develop Server production power on sequence control logic by CPLD / FPGA
3.Implement new technology and design concept in CPLD / FPGA
Design test plan, development specification, and issue tracking.
Overview
We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration.
Key Responsibilities
Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI).
Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction.
Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs.
Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput.
Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines.
Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.
1.Familiarity with VHDL/Verilog coding and FPGA/CPLD design flow is a must
2.Familiarity with FPGA/CPLD design in server application and bus protocols including I2C / power sequence / SPI / LPC / SGPIO / I2C switch/ UART / PWM / eSPI
3.Familiarity with Lattice/Altera EDA design tool.
4.Strong HW and x86 architecture knowledge.
5.Integration and simulation experience
6.Issue Fail symptom Anlayze and Tracker
※依學經歷、工作年資敘薪