【Customer Engineering Account Management】
(1)Meet and exceed customer’s expectation of advanced package engineering in terms of quality, cost and delivery
(2)Offer industrial leader’s advanced package solutions and services through integration of package and process development
【Project management】
(1)Project phase in schedule arrangement and follow up
(2)SWR arrangement ,schedule follow up, negotiation…etc.
(3)PKD/PMD creation (PLM)
(4)Reliability arrangement
【Team Work】
(1)To optimize resource allocation
(2)Enhance teamwork in 360° including customer, supplier and our colleagues
(3)Develop self and others
1. 薪資依學歷、科系、相關工作經驗、專業證照、特殊專長與語言能力綜合核敘;
2. 資深人員薪資另議。
This role will lead the Package Design Project with R&D team members and deliver advanced and innovative packaging resolutions to clients. (Flip-Chip)
1.Package RFQ and structure & BOM selection.
2.Direct material evaluation and survey.
3.FA and Reverse Engineering.
4.Package design rule maintain & update.
5.Advance products design / NPI projects development.
6.Research & setup package roadmap / material roadmap.
執行晶圓級封裝AOI製程專案開發、製程整合、良率改善及缺陷分析
詳細職責如下:
1. Maintaining process flow and recipes on MES, and tools and recipes on RMS.
2. Handling abnormal cases on MES and conducting daily yield analysis.
3. Supporting New Product Introduction (NPI) and Design of Experiments (DOE), and preparing summary reports.
4. Developing and implementing process improvements to enhance yield and productivity.
5. Conducting root cause analysis for defects and collaborating with cross-functional teams to resolve process-related issues.
此職務需日夜輪班 (做二休二,約每三個月日夜輪調一次)
日班上班時間:07:20~19:30 (中間休息2小時10分,實際工時10小時)
夜班上班時間:19:20~07:30 (中間休息2小時10分,實際工時10小時)
* 熟悉半導體晶圓級製程或具備跨部門溝通經驗尤佳。
*實際薪資依學歷、科系、相關工作經驗、專業證照、特殊專長與語言能力綜合核敘。
*資深人員薪資另議。
Main work content:
1. Fan-out structure/ material/ process flow design
2. Fan-out RDL layout drawing review
3. Packaging direct material survey, evaluation, improvement & qualification
4. Design rule establishment & maintenance
5. Package failure analysis
6. Coordinate & lead project in design portion & co-work with process, integration & simulation teams
7. Direct communication with customers
* 薪資依學歷、科系、相關工作經驗、專業證照、特殊專長與語言能力綜合核敘。
* 資深人員薪資另議。
1. To improve device yield &CIP in order to meet customer request and customer service.
2. Identify and solve process and device problems.
3. Support for customer visit and audit.
A. Package design
1. Package RFQ for cost estimation
2. New device package feasibility & technical risk assessment
3. Package structure, BOM design
4. Package design rule setup & update
5. Coordinate DR0 design review meeting
6. PKG structure confirmation after setup
B. Package research & development
1. Research & setup package roadmap / material roadmap
2. New package development
3. New material survey & capability development
4. Setup direct material purchase specification
5. Technical benchmark with competitors (Reverse engineering)
1. Ensure PKG design is optimized with SI/PI/Thermal requirements.
2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model.
3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools.
4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design.
5. Provide the Substrate manufacturing process and material property.
6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.
7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis.
8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB.
9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain.
10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations.
11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements.
12. Familiar with assembly and substrate manufacturing process is a plus.
13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent.
14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus.
15. Working with ASIC/HW/Production team.