1. Ensure PKG design is optimized with SI/PI/Thermal requirements.
2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model.
3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools.
4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design.
5. Provide the Substrate manufacturing process and material property.
6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.
7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis.
8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB.
9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain.
10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations.
11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements.
12. Familiar with assembly and substrate manufacturing process is a plus.
13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent.
14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus.
15. Working with ASIC/HW/Production team.
【產品範疇】
1.DDI / TP / TDDI/ TCON/ Power等顯示相關產品
【工作內容】
1. SI/PI/EM issue solving, performance optimization, and design rule development
2. Chip/PKG/Board simulation and measurement for SI/PI/EM issue.
3. Co-work with system engineers, IC designers, and customers on product design-in tasks.
THE ROLE
The Lead Signal Integrity Engineer is a technical leader responsible for advancing Isola’s laminate materials to meet and exceed high-speed electrical and signal integrity (SI) performance requirements. This role provides mentorship and direction to the Signal Integrity team in Taiwan, drives innovation in SI test methodologies, and ensures strong technical engagement with global OEMs. The Lead serves as a recognized authority in SI, bridging customer needs with material performance and representing Isola in the high-performance electronics community.
KEY RESPONSIBILITIES:
Customer-Facing Technical Support:
• Lead technical engagement with OEMs and direct customers on high-speed laminate characterization.
• Act as primary technical contact for SI-related design validation and adoption cycles.
• Oversee the creation of technical reports, white papers, and collateral for internal and external use.
Strategic & Technical Leadership:
• Define and develop advanced SI measurement, modeling, and simulation methodologies.
• Collaborate with Product Management, R&D, and Sales to ensure alignment of SI capabilities with product strategy.
• Represent Isola as a thought leader through publications, conferences, and industry forums.
Organizational Management:
• Mentor, guide, and grow the Taiwan-based Signal Integrity Engineering team.
• Establish scalable, cost-effective SI test methods that accelerate R&D and customer response.
• Drive alignment with global Application Engineering teams to ensure best-in-class technical service.
Technology & Standards Thought Leadership:
• Maintain expertise in SI methods, PCB processing effects, and high-speed digital design requirements.
• Contribute to industry standards development and support customer forums on SI requirements.
QUALIFICATIONS & EXPERIENCE
• 8+ years of experience in signal integrity engineering, PCB laminates, or high-speed design.
• Expertise in VNA measurements, probing techniques, and advanced SI methodologies.
• Experience with PCB manufacturing and processing effects on SI performance.
• Demonstrated leadership and mentoring experience.
• Proven record of technical publications, white papers, or conference presentations.
EDUCATION
• PhD or Master’s in Electrical Engineering or related field required.
OTHER CONSIDERATIONS
• Fluent in English – required for global communication and technical documentation.
• Proficiency in Mandarin Chinese – strongly preferred for engagement with Taiwan/China teams and customers.
• Ability to travel regionally and globally as needed.
1. Electromagnetic simulation and electrical modeling by using Ansys EM suite.
2. SI/PI high frequency / high speed signal integrity / power integrity / antenna radiation with Ansys EM/ADS systems.
3. 3D full wave FEM/FDTD large-scale simulation and validation with EMpro and HFSS HPC.
4. Signal emulation and performance simulation in PCB/Substrat of optical module.
主要產品為低軌道衛星地面站與5G毫米波基站,產品型態可分為設計代工與生產代工,具體工作內容如下:
陣列天線設計代工
1. 主動相位陣列天線設計與模擬
I. 電路板材挑選與疊構設計評估
II. 單元天線之設計與模擬
III. 陣列天線之設計與模擬
IV. 功率分配器設計與模擬,整合至陣列天線
V. 相移器晶片與陣列天線之整合
VI. 主動相位陣列天線控制單元設計
2. 主動相位陣列天線實作與量測
I. 電路板製作與打件
II. 天線控制單元驗證
III. 陣列天線輻射場型校正量測與最佳化,驗證波束指向準確性
IV. 產線用快速陣列天線量測系統設計與驗證
陣列天線生產代工
1. 主動相位陣列天線實作與量測
I. 基於客戶設計,提出製程改善建議
II. 電路板製作與打件
III. 陣列天線特性量測,包含天線控制單元驗證與輻射場型量測
微波被動電路與射頻收發機設計
1. TX/RX射頻電路規畫及設計
2. 分析及挑選適合材料
3. 畫電路線路圖及與電路佈局工程師溝通、協調並完成電路及送件完成PCB製作
4. 與機械工程師溝通並完成電路板與機械結構的組裝及量產可行性評估
5. 與軟/韌體工程師合作完成整體系統運作及生產測試
6. 電路板製作與打件
7. 電路板測試驗證及除錯分析
以上模組會整合進低軌道衛星地面站或5G毫米波基站
1. 射頻收發機與陣列天線整合設計
2. 整機組裝,系統特性測試驗證與除錯分析
產品驗證完成導入量產,客戶溝通與專案進行
1. 統籌公司內部資源,達成專案需求
2. 與客戶溝通技術問題,並轉知公司內部團隊研究改良
3. 協助產品導入量產,各項文件建立及產出
4. 出差至客戶處報告專案進度
[General Summary]
As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.
We are seeking a PCB Design Engineer with strong theoretical foundation and simulation driven design methodology to lead high speed board level development. You will be responsible for defining and verifying board level electrical design, ensuring optimal signal integrity across multiple high speed interfaces. You will be supported by experienced layout engineers capable of implementing your design guidance and constraints, allowing you to focus on PCB circuit design and system validation. This position offers the opportunity to build structured PCB design practices, improve team capability, and drive electrical excellence through direct ownership of simulation and cross team collaboration.
[Responsibilities]
★ Lead system level PCB electrical design for interfaces such as LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet.
★ Define PCB stack up and routing strategy to meet signal integrity objectives.
★ Perform circuit level simulations using tools such as PSpice.
★ Own schematic level electrical planning and define layout constraints for critical signal groups.
★ Provide guidance to supporting layout engineers to ensure adherence to electrical rules and best practices.
★ Correlate simulation results with lab measurements and assist in electrical issue root cause analysis.
★ Document simulation methodology constraint guidelines and validation reports.
★ Occasional business travel across APAC and other regions may be required.
[Minimum Qualifications]
★ Familiarity with differential and single ended routing across LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet.
★ Proficiency with layout tools such as Allegro.
★ Exposure to EMI mitigation techniques and hands on experience in EMI pre compliance testing.
★ Demonstrated ability to lead layout teams or mentor junior engineers in constraint based PCB design.
★ Ability to create structured documentation and design guidelines to scale internal processes.
★ Strong debugging and problem solving skills with working knowledge of firmware and software to support system level root cause analysis.
★ Comfortable working in a globally distributed, cross-disciplinary engineering team.