「SoC/ASIC/IP digital design engineer」的相似工作

Job Contents · 3+ years of EDA flow expertise. · Responsible for timing closure / signoff flow development including timing closure methodology development, flow automation. .SDC validation , domain knowledge enhancement · Project support/execution & collaboration with EDA vendors. · STA sign-off flow/scripts/environment development for advanced process nodes.

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責IP設計流程之Front-end Engineer之職缺。 【將負責的工作內容】 1. Develop CAD utility for design automation -Library characterization of SRAM/STD timing, power and quality assurance. -SRAM compiler design, gds tilling, netlist tilling. -Support RD to fixed EDA issue. 2. Experience in script programming -linux shell/ TCL / Perl script 【條件與特質】 1. 碩士以上電子、電機、電信、電控、資工等相關科系 2. 擅長工具:各種IC設計自動化的工具皆可,C,C++,TCL,CSH,PERL等程式語言 3. 具備程式能力

SOC-NxSOC(next generation) team is hiring both junior and senior engineers, whose work scope is implement methodology development and PPA optimization from RTL to GDS. Join us, you will work together with expertise in all these areas; you will not only work for SOC development, but also enjoy and experience for all related products: smart phone/ tablet/ wearable/automotive etc.; you will work for the most advanced process/technology, the best chip in the world. What you'll be doing: - Methodology development at all stages, including synthesis, PnR, timing, IR, PV etc - PPA optimization What we need to see: - BSEE, MSEE is preferred - Project experience in IC design implementation - Courses taken in circuit design, digital design - Hand-on experience in EDA software from Synopsys (DC/FC-fe/FC-be/ICC2/PT/Formality), Cadence (Innovus), Ansys(Redhawk/RHSC) is preferred Ways to stand out from the crowd: - Proficient user of Perl, Python or TCL is preferred - Excellent English communication skill

1. Participate in digital design specification, architecture definition, and microarchitecture planning. 2. Conduct FPGA prototyping, testing, and debugging of digital IP designs. 3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration. 4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.

主要職務: FPGA電路研發 • 負責 FPGA Verilog程式設計、開發、模擬、除錯與驗證 • 閱讀並理解英文技術手冊（datasheet、user guide、application note） • 撰寫 RTL（Verilog / VHDL / System Verilog）模組，整合硬體與韌體 • FPGA 與高速介面設計 (GTH / Ethernet / DDR 等) • 協助Pin Assignment、時序約束 • 撰寫測試平台與 testbench，並進行波形分析 • 撰寫與維護開發相關文件 工作環境: 一般辦公空間 工作時間: 8:00~9:30彈性上班，5:00~6:30彈性下班，周休2日，無須輪班

負責數位IP演算法, 與數位工程師共同開發影像處理電路

1. 負責IC佈局和佈線的設計和開發 2. 實現佈局和佈線的細節設計和調整 3. 與相關的團隊成員合作，確保佈局和佈線設計能夠達到高效率和性能 4. 配合其他工程師進行相關的測試、分析和報告 5. 解決相關佈局和佈線問題 6. 修改維護 Command file 7. 使用CADENCE VIRTUOSO或LAKER等工具進行IC佈局和佈線的驗證

(1)Must have BS in CS/EE of relevant experience in IC design field. (2)Familiar with IC design flow, placement and route (P&R), and layout. (3)Circuit knowledge and logic design relevant experience would be a plus.

1. 產線靜電防護(ESD)量測計畫制定與執行 2. 靜電防護測試與分析結果判讀 3. 客戶問題處理與溝通 4. 生產線直接人員作業流程檢視與教育訓練‧ 5. 生產線稽核、6S稽核檢視及改善 6. 協助主管異常調查與改善

1. 類比電路設計開發 2. 感測器元件開發與整合 3. 具CIS影像感測器相關類比IC電路設計經驗者佳

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1. Logic NVM, SONOS 記憶體電路開發設計(Array, Decoding, Sense Amplifier等電路) 2. 記憶體電路整合開發設計。

1.Work with team members and apply design techniques to work on different phases of complex logic design for ASIC/SOC project. 2. Working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc.

1. FrontEnd flow development. 2. Project support and consultant. 3. Develop CAD utility, design automation 4. Work with different process nodes, develop the design flow and methodology

1.SERDES CMOS Circuit Design ( HDMI,DisplayPort, or USB3.0 ). 2.All Digital PLL Circuit Design.

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

1. 負責 FPGA 功能驗證、程式開發、測試、除錯及維護 2. 撰寫 Testbench 進行模擬驗證 3. 具 I2C、SPI 通訊介面運作經驗者 4. 熟悉 Xilinx RFSoc 架構與設計 5. 熟悉 Linux Driver 實作經驗

數位IC設計

【工作內容】 • 我們正在尋找具備先進製程經驗的 IC Layout 工程師，加入團隊後可以參與高階SoC /Analog IP 的實體實現，並負責以下工作： -Mixed-Mode FinFET Layout 設計與繪製，確保電路佈局在效能、面積與可靠性之間取得最佳平衡。 -進行 FinFET 製程相關的 DRC / LVS / ERC 驗證，確保設計符合法規與 Foundry 要求。 -熟悉 XRC & EM/IR 分析流程，進行可靠性評估，並針對潛在問題提出改善方案。 【職務條件】 • 必備條件：具備 FinFET 製程經驗，能獨立進行版圖設計與驗證。 -具備類比電路佈局經驗，了解電路特性與佈局考量，能與設計工程師密切合作。 -具備良好的溝通能力與團隊合作精神，能在專案時程內交付高品質成果。