Overview
We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration.
Key Responsibilities
Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI).
Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction.
Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs.
Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput.
Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines.
Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.
The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request.
What a typical day looks like:
1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design.
2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters.
3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development.
4. Designing validation plan and development spec.
5. Debugging platform and systems issues.
The experience we are looking to add to our team:
1. 3-10 years of working experience in Firmware development.
2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices.
3. Experience with I2C, SPI, LPC, UART, PCIe protocol design
4. Experience with verification methodologies, RTL and gate level simulations and debug.
5.Good problem-solving skills.
The information we collect:
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1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance
2.Develop Server production power on sequence control logic by CPLD / FPGA
3.Implement new technology and design concept in CPLD / FPGA
Design test plan, development specification, and issue tracking.
Key responsibilities:
• Perform IC design of FTDI products
• Perform Verilog RTL design to meet product specifications and requirements
• Perform front-end verification using UVM methodology
• Work with Systems and Software engineers on FPGA verification
• Perform Logic Synthesis, Static Timing Analysis
• Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation
• Work with Physical designer to achieve timing closure
• Work with test team in debugging production test issues
• Help debug & correct any functional issues found in taped-out devices
• Participate in design reviews, support ISO processes and documentation
Additional responsibilities:
a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business.
b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices.
Knowledge and skill requirements:
• Degree/Master in Electrical/Electronic Engineering
• 5 years or above experience in the area of digital IC design
• Working experience from design to tape-out are essential
• Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification
methodology , Logic Synthesis, DFT, ATPG, Timing Closure
• Experience in using EDA tools from Cadence, Synopsys
• Knowledge and working experience in one or more of the following:
o Digital and mixed-signal design
o USB interface products
o Knowledge in connectivity technology such as USB, UART, SPI, I2C
o Project Management
Working conditions:
Working conditions are normal for an office environment.
Work requires willingness to work a flexible schedule.
1. 具 0~2年數位晶片設計,或有 0~5年類比晶片設計工作經驗。
2. 具備基本數位和類比電路知識,熟習標準晶片設計流程。
3. 熟習業界常用EDA tools, 或Matlab/ Simulink。
4. 研習過CMOS or BiCMOS 類比設計電路課程,對放大器有基礎認識。
5. Experience in these areas is preferred:
* BiCMOS or CMOS high-speed (>20Gb/s) circuit, Linear electrical amplifier &
equalizer, High-speed (>25G) CDR/PLL/SerDes.
* Linear optical laser driver & receiver (TIA + linear amplifier)
本職位負責類比IC電路的設計、驗證和除錯。這是一個高度技術性的職位,對公司的產品開發至關重要。我們正在尋找一位熱愛類比IC設計並具有相關經驗的人才,以推動公司的技術創新和發展。
如果您對這個職位感興趣,請投遞您的履歷表,我們立即與您聯繫。
1. Participate in digital design specification, architecture definition, and microarchitecture planning.
2. Conduct FPGA prototyping, testing, and debugging of digital IP designs.
3. Collaborate closely with analog/mixed-signal design teams, firmware engineers, and system engineers to ensure successful product integration.
4. Develop, implement, and verify RTL code (Verilog/SystemVerilog) for high-speed Serdes interfaces including USB, DP, HDMI, DDR and PCIe.
The Team and Role:
The Embedded SW Test team’s mission is to strengthen the firmware validation process and fully automate the test procedures. We develop truly innovative test instruments and tools to achieve this goal.
The FPGA Firmware Developer /Test Engineer is responsible for designing, implementing and testing FPGA firmware used for test automation.
Your Contribution:
Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviors you’ll need for success at Logitech. In this role you will:
• Participate in the development of a test automation framework
• Leverage your technical hardware and software skills to design & implement the testing infrastructure
• Evaluate and develop new FPGA modules to automate the integration test suites for our next generation devices
• Develop, run and maintain automated scripts to prove product conformity regarding component specification
• Improve processes or propose improvement where’s applicable