「CMOS Image Sensor Analog Design Engineer」的相似工作

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

1.設計高速 SERDES 電路及相關Analop IP (TX,RX,PLL,I/O....) 2.熟悉以下電路尤佳 OSC, TX, DDR, Equalizer, PLL, DLL, CDR, Memory, Buck .

1.SERDES CMOS Circuit Design ( HDMI,DisplayPort, or USB3.0 ). 2.All Digital PLL Circuit Design.

Are you an experienced IC design expert/architect with a passion for pushing the boundaries of technology? MediaTek, a leading semiconductor company, is currently seeking talented professionals to join our team! Work location: Hsinchu/Taipei/San Diego/San Jose

Job Description: As a team member of analog product business group, this role will support Analog IC circuit design of mixed-signal ICs, such as sensors, motor drivers, data converters. Key Responsibilities: 1. Co-work with talented design teams to develop high performance sensor related integrated circuits and products, such as Hall effect sensor, temperature sensor. 2. Contribute to chip architecture and circuit design decisions 3. Collaborate with validation, product engineering and test engineering teams to enable successful transfer to production 4. Also, will be responsible for circuit requirements definition, design, simulation and analysis, layout/test support, documentation and customer support for sensor applications. Qualifications: 1. Demonstrate strong analytical and problem-solving skills 2. Strong time management skills that enable on-time project delivery 3. In depth working experience with Cadence composer and Virtuoso, Spectre, HSpice and mixed-signal design flow. 4. Experience in lab measurement and equipment. 5. Self-starter. Passionate about creative work. Good communication skills and team player. Able to take the initiative and drive for results.

1. 觸控IC、TDDI或指紋辨識 IC 開發經驗 2. ADC或sensor IP 開發經驗 3. TFT-LCD或OLED Display driver IC 開發經驗 4. Charge pump、LDO、Source driver、Gate driver、High speed interface、OSC、BGR 相關開發經驗 5. 工作地點：【台南、新竹、台北】 以上其中任何一項相關者佳。

【職位描述】 設計RVI公司新創的光通訊引擎(Optical Engine)類比電路設計工程師，負責設計、開發、測試、優化和調試類比電路及系統，產品矽中介層、玻璃中介層與高階基板。負責從概念到生產的電路設計，確保光引擎達到品質和性能標準。 【主要職責】 1.設計和開發創新的類比電路和系統，應用於光引擎和相關技術領域。 2.測試、優化和調試類比電路，確保其性能符合設計規範和功能需求。 3.與跨部門團隊合作，包括系統工程師、軟體工程師、光學工程師及其他專業人員，共同實現產品開發目標。 4.與客戶密切合作，理解其需求並提供技術支持和解決方案。 5.制定和執行測試計畫，分析測試數據，並提出改進建議。 6.保持對最新技術趨勢的了解，並將其應用於產品設計中以提升競爭力。 Position Description: As an Analog Circuit Design Engineer at RVI, you will be a key contributor to the development of our next-generation Optical Engine. You will be responsible for designing, developing, testing, optimizing, and debugging analog circuits and systems used in advanced optical communication modules, including silicon interposers, glass interposers, and high-end substrates. This role spans from initial concept to mass production, ensuring the performance and quality of the optical engine meet industry standards. Key Responsibilities: 1.Design and develop innovative analog circuits and systems for optical engines and related applications. 2.Test, optimize, and debug analog circuits to ensure performance meets design specifications and functional requirements. 3.Collaborate with cross-functional teams, including system engineers, software engineers, and optical engineers, to achieve product development goals. 4.Work closely with customers to understand their requirements and provide technical support and tailored solutions. 5.Develop and execute test plans, analyze test data, and propose design improvements. 6.Stay updated on emerging technologies and incorporate relevant advancements into circuit design to enhance product competitiveness.

RF及類比IC設計與整合： (1) VCO, PLL (2) PA, LNA, Mixer

1. PLL design 2. High speed receiver design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 3. High speed transmitter design (1.5Gbps/4Gbps/5.4Gbps/8.1Gbps/12Gbps) 4. eDP receiver 5. V-by-One receiver 6. MIPI D-PHY 7. HDMI Receiver 8. HDMI Transmitter 9. LCD P2P interface Transmitter 10. LDO and DCDC design 工作地點:新竹/台南

*大學月薪33800元 / 碩士月薪38600元 1.申請與執行研究計畫。 2.負責報帳、經費申請、物品建檔等行政工作。 3.操作並維護計劃或實驗相關的設備與儀器。 4.協助資料收集和資料分析。 5.編輯、撰寫計畫報告書。

1、Mixed signal IC design and verification 2、Familiar with analog circuit designs including OPAMP/PGA, Analog active filter, ADC, DAC, level shifter, CDR, charge pump, PLL, bandgap reference 3、Co-work with board-level designers to analyze power and signal integrity of PCB. 4、Transmit signal & Noise characterization and analysis 5、Experience Preferred： 3-year work experience in the following fields High-speed serdes TX/RX application Pipeline ADC / SAR ADC 6.、Master or Ph.D. degree in EE

1.ADC/LVDSTRX/LVDSTX/MIPIRX/MIPITX/DC2DC/LDO/Charger/Power IC 2.類比電路特性量測 3.Analog/Mixed signal integrated circuit design

(1)Circuit Design. (2)Circuit Simulation. (3)Layout Verification. (4)Silicon verification and debugging. (5)Transfer design to production.

Do you expect to learn more the complete methodologies/solutions of design, implementation and analysis for a high-performance, power-efficient and area-effective chip developments? Do you also expect to explore the AI-driven solutions to accelerate chip design and improve efficiency throughout the design flow with AI-powered EDA tools? As part of our teams, you’ll have an opportunity to accordingly study, explore and design next-generation methodologies/solutions as follows. (1) Develop, maintain and optimize advanced methodologies for Frontend, Backend and Mixed-signal Design and implementation flows with the integrations of many corresponding EDA tools (Synopsys/Cadence/Siemens/Xilinx, ..., etc.) (2) Study, Explore and evaluate AI-driven design and implementation methodologies Currently, we expected this candidate is familiar with or interested in the related skill developments as follows. (1) Analog design flow and methodologies (Speed-up/Optimized simulation, mixed-signal co-simulation, EM/IR, Reliability Analysis, …, etc.). Knowledge of digital design flow using EDA tools (Synopsys, Cadence, Siemens (Mentor), …, etc.) is a plus (2) Programming/Scripting language like Perl, TCL, Python, C/C++, PERC, ..., etc. for flow automation (3) Be able to individually study and implement feasible solutions to resolve technical issues occurring in design and implementation flows. In our department, through kinds of flow developments and the related technical issue resolving, the following skill sets will finally be captured. (1) Extensive tool knowledge and experience for many different kinds of EDA tools and flow integration (Synopsys/Cadence/Siemens/Xilinx, …, etc.) used for Analog/Digital/FPGA Design and prototyping (2) Work with analog/digital design teams to coordinate a complicate project including Analog/Digital Designs for successfully tape out (3) Extensive AI-driven Analog/Digital/System Design and implementation flow We believe this position can be a great opportunity to extend your cross-fields IC design capabilities to include Analog, Digital and even System level designs for handling more complicate SoC design in the future.

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表：https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/GPU-Compiler-Development-Engineer--up-to-Sr-Staff--Hsinchu-_3057774 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/GPU-Compiler-Development-Engineer--up-to-Sr-Staff--Hsinchu-_3057774 【Job Description】 The largest provider of premium mobile SoC (system on chip) solutions. Adreno GPU has been driving the mobile industry toward rich graphics and gaming experience on smartphones. Now its power efficient GPU technology becomes fundamental to enable some new exciting markets beyond the smartphone like VR/AR, IoT, AI, drone, autonomous driving. GPU compiler is a key component of overall graphics technology, especially in terms of its influence on application’s performance on GPU. We are looking for talented engineers to create world class GPU compiler products to enable high performance graphics and compute with low power consumption. 【Responsibilities】 This position will be responsible for research, development and delivery of Qualcomm's Adreno GPU compiler products to our worldwide customers. At same time, there will be opportunities to influence GPU hardware design based on experience on how our GPU compiler has been used by real world users. 【Minimum Qualifications】 * Good C/C++ programming skills * Good communication skills and teamwork spirit, reliable and self-motivated 【Preferred Qualifications】 * Compiler development. For example, LLVM or GCC * Graphics knowledge or graphics/game software development * DirectX, OpenGL/Vulkan, OpenCL, or CUDA compiler development * D3D/OpenGL/Vulkan/OpenCL/CUDA driver development

1.Design and maintain analog circuits 2.Survey and maintain design processes 3.Survey and maintain design tools and flow 4.Help training junior engineers 5.Debugging and measuring chip

1.LPDDR4/DDR4/DDR3 Mixed signal SERDES/PLL相關開發工作 2.Mixed signal SERDES RTL behavior analysis and implement,熟悉HSPICE 並具備 std cell design flow基礎佳

******以下有兩個不同的職位****** 【Analog IC Designer (DRAM IO) - 竹北】 工作內容 1. IO 設計. 2. DDR RX/TX 設計. 3. DDR 類比. 4. 擁有 DRAM IO 設計經驗，有 DDR5 以上經驗者尤佳。 擅長工具: HSPICE、Python、Laker、ADP、Custom Compiler 1. 學習過電子學、電磁學、電路學、工程數學等基本課程且成績優良。 2. Familiar with Analog Circuit Design 【 Analog IC Designer (Integration) - 竹北】 工作內容 1. Analog IP top integration, including projects of SSD/UFS/eMMC/SD 等。 2. 基本類比電路設計概念，例如 LDO、DCDC、BANDGAP、Voltage Detector 或 PLL、ADC 等。 3. 協助故障樣品分析與 IC 測試。 其他條件 1. 熟悉量產相關知識與經驗者佳。 2. 類比設計經驗超過 3 年。

Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Chip Planning • Project Schedule / Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Top Level connections • Signal matching / sensitive nets shielding technique • Chip power / ground planning • Integration of Analog top with Auto-Placement-Routing • Pad / ESD rule and routing / connection • Database DRC & LVS verifications on either DIVA or Dracula basis • Chip Tape-out in accordance with company’s Tape-out Procedure • Positive Attitude Qualifications: • 3+ years Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable