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Job Mission
Represent manufacturing and act as gatekeeper from manufacturing to D&E function
Add value in overall manufacturing processes such as forming, machining, joining, and assembling
Job Description
Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat
Identify gaps and drive assigned process improvement projects and successful delivery
Initiate and drive new procedure changes and projects
Develop and maintain networks across several functional stakeholders
Prioritize works and projects based on business situation
Transfer knowledge and train colleagues on existing and newly introduced products
Education
Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics)
Experience
3-5 years working experience in design engineering
Personal skills
Show responsibility for the result of work
Show proactive attitude and willing to take initiative
Drive for continuous improvement
Able to think outside of standard processes
Able to work independently
Able to co-work with different functional stakeholders
Able to demonstrate leadership skills
Able to work in a multi-disciplinary team within a high tech(proto) environment
Able to think and act within general policies across department levels
Diversity and inclusion
ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company.
Need to know more about applying for a job at ASML? Read our frequently asked questions.
- Job Description -
We are looking for a highly motivated SI/PI Engineer to join our technical team.
You will play a key role in simulating and analyzing high-speed signal and power integrity in next-generation probe card systems.
Using advanced 3D modeling and full-wave simulation tools, you will help push the boundaries of traditional limitations and enable breakthrough designs supported by our proprietary processes.
- Responsibilities -
• Develop and optimize 3D SI/PI models for high-speed test interfaces
• Perform system-level simulations using tools such as Ansys HFSS, SIwave, ADS
• Explore new layout and structural ideas enabled by our in-house fabrication capabilities
• Evaluate the impact of materials and design configurations on SI/PI performance
• Collaborate with R&D and manufacturing teams to improve PDN and signal routing reliability
- Qualifications -
• Master’s degree or above in Electrical Engineering, Electronics, Telecommunications, Physics, Materials Science, Mechanical Engineering, or related fields
• 1+ years of experience in SI/PI simulation and modeling; background in probe card, PCB, or advanced packaging is a plus
• Proficient in 3D modeling and simulation tools (e.g., HFSS, CST, COMSOL)
• Strong analytical thinking and self-driven problem-solving capabilities
• Good command of technical English (reading and documentation)
- What We Offer -
• Opportunity to develop next-generation probe card platforms that lead the industry
• Collaborative and innovation-driven work environment with Taiwan & U.S. teams
• Fast learning curve, strong technical exposure, and room for individual impact
1. Ensure PKG design is optimized with SI/PI/Thermal requirements.
2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model.
3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools.
4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design.
5. Provide the Substrate manufacturing process and material property.
6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.
7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis.
8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB.
9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain.
10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations.
11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements.
12. Familiar with assembly and substrate manufacturing process is a plus.
13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent.
14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus.
15. Working with ASIC/HW/Production team.
[General Summary]
As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.
We are seeking a PCB Design Engineer with strong theoretical foundation and simulation driven design methodology to lead high speed board level development. You will be responsible for defining and verifying board level electrical design, ensuring optimal signal integrity across multiple high speed interfaces. You will be supported by experienced layout engineers capable of implementing your design guidance and constraints, allowing you to focus on PCB circuit design and system validation. This position offers the opportunity to build structured PCB design practices, improve team capability, and drive electrical excellence through direct ownership of simulation and cross team collaboration.
[Responsibilities]
★ Lead system level PCB electrical design for interfaces such as LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet.
★ Define PCB stack up and routing strategy to meet signal integrity objectives.
★ Perform circuit level simulations using tools such as PSpice.
★ Own schematic level electrical planning and define layout constraints for critical signal groups.
★ Provide guidance to supporting layout engineers to ensure adherence to electrical rules and best practices.
★ Correlate simulation results with lab measurements and assist in electrical issue root cause analysis.
★ Document simulation methodology constraint guidelines and validation reports.
★ Occasional business travel across APAC and other regions may be required.
[Minimum Qualifications]
★ Familiarity with differential and single ended routing across LPDDR4/5, USB 3.x, SDIO 3.x, MIPI and Ethernet.
★ Proficiency with layout tools such as Allegro.
★ Exposure to EMI mitigation techniques and hands on experience in EMI pre compliance testing.
★ Demonstrated ability to lead layout teams or mentor junior engineers in constraint based PCB design.
★ Ability to create structured documentation and design guidelines to scale internal processes.
★ Strong debugging and problem solving skills with working knowledge of firmware and software to support system level root cause analysis.
★ Comfortable working in a globally distributed, cross-disciplinary engineering team.
THE ROLE
The Lead Signal Integrity Engineer is a technical leader responsible for advancing Isola’s laminate materials to meet and exceed high-speed electrical and signal integrity (SI) performance requirements. This role provides mentorship and direction to the Signal Integrity team in Taiwan, drives innovation in SI test methodologies, and ensures strong technical engagement with global OEMs. The Lead serves as a recognized authority in SI, bridging customer needs with material performance and representing Isola in the high-performance electronics community.
KEY RESPONSIBILITIES:
Customer-Facing Technical Support:
• Lead technical engagement with OEMs and direct customers on high-speed laminate characterization.
• Act as primary technical contact for SI-related design validation and adoption cycles.
• Oversee the creation of technical reports, white papers, and collateral for internal and external use.
Strategic & Technical Leadership:
• Define and develop advanced SI measurement, modeling, and simulation methodologies.
• Collaborate with Product Management, R&D, and Sales to ensure alignment of SI capabilities with product strategy.
• Represent Isola as a thought leader through publications, conferences, and industry forums.
Organizational Management:
• Mentor, guide, and grow the Taiwan-based Signal Integrity Engineering team.
• Establish scalable, cost-effective SI test methods that accelerate R&D and customer response.
• Drive alignment with global Application Engineering teams to ensure best-in-class technical service.
Technology & Standards Thought Leadership:
• Maintain expertise in SI methods, PCB processing effects, and high-speed digital design requirements.
• Contribute to industry standards development and support customer forums on SI requirements.
QUALIFICATIONS & EXPERIENCE
• 8+ years of experience in signal integrity engineering, PCB laminates, or high-speed design.
• Expertise in VNA measurements, probing techniques, and advanced SI methodologies.
• Experience with PCB manufacturing and processing effects on SI performance.
• Demonstrated leadership and mentoring experience.
• Proven record of technical publications, white papers, or conference presentations.
EDUCATION
• PhD or Master’s in Electrical Engineering or related field required.
OTHER CONSIDERATIONS
• Fluent in English – required for global communication and technical documentation.
• Proficiency in Mandarin Chinese – strongly preferred for engagement with Taiwan/China teams and customers.
• Ability to travel regionally and globally as needed.