「DFT Engineer」的相似工作

At NVIDIA, our innovation knows no bounds. Our team is at the forefront of groundbreaking technologies, and we are looking for an exceptionally dedicated Test Development Engineer to join us in Taipei, Taiwan. If you are passionate about automation, quality, and innovation, this could be the perfect opportunity for you! What You’ll Be Doing: Design, develop, and maintain automated test frameworks and pipelines for server firmware and software. Implement and enhance end-to-end test automation to improve coverage, efficiency, and reliability. Collaborate closely with PM, development, tools, and AE teams to understand requirements and ensure comprehensive test coverage. Complete tests for server firmware and software to ensure high product quality and meet project schedules and customer needs. Support factory test processes to ensure firmware is robust enough for manufacturing. Analyze test results, debug failures, and provide actionable insights to improve product quality and reliability. Contribute to the continuous improvement of testing strategies, tools, and processes to drive innovation and quality. What We Need to See: Bachelor’s or Master’s degree in Computer Science, Engineering, or a related field, or equivalent experience. 5+ years of hands-on experience in test development, firmware development, automation, or software engineering. Strong experience with server firmware and corresponding test methodologies. Proficiency in crafting and implementing automated test frameworks and CI/CD pipelines using tools like Python, Java, Jenkins, and Robot Framework. Proven understanding of server hardware, BIOS/UEFI, BMC, and related firmware components. Experience with AI coding tools (e.g., Cursor, Windsurf, GitHub Copilot) and integrating them into test workflows. Excellent problem-solving, communication, and collaboration skills. Passion for quality, automation, and innovation in a fast-paced, dynamic environment. Ways to Stand Out from the Crowd: Track record of driving automation initiatives or process improvements within a technical team. Ability to communicate technical findings and recommendations clearly to both technical and non-technical collaborators. Experience with multi-functional collaboration and working in distributed or global teams. Demonstrated ability to apply AI/ML techniques to optimize or innovate test automation workflows and improve testing efficiency.

歡迎2026年畢業並正在找尋研發替代役的同學申請! Direction 1: System Design Power Validation Engineer Direction 2: PCB Layout Engineer Direction 3: System Application Engineer What you'll be doing: • Collaborate with system design, hardware, and power engineering teams to participate in end-to-end design, validation, and optimization of hardware products (such as GPUs, AI accelerators, server platforms, etc.) • Responsible for circuit schematic design and PCB layout using EDA tools (such as Altium, Cadence, Mentor Graphics) for multilayer high-speed board design and optimization • Perform PCB design reviews, assist in resolving signal integrity, power integrity, EMI/EMC issues to improve design quality and manufacturability • Participate in board bring-up, debugging, power testing, and performance validation of hardware prototypes, helping to ensure optimal power efficiency under varying operating conditions • Write and maintain design, validation, and test documentation, including but not limited to design specifications, validation reports, and test plans • Work closely with cross-functional teams to continuously improve design processes and enhance product innovation and competitiveness What we need to see: • Hold a Master of Science/Ph.D in Electrical Engineering or related field • Familiar with circuit schematic design and PCB layout processes, and basic proficiency with EDA tools (such as Altium, Cadence Allegro/OrCAD, Mentor PADS, etc.) • Strong interest in power management, DC-DC converters, signal integrity, and high-speed digital design is a plus • Good debugging, analysis, and problem-solving skills; able to work independently or within a team to resolve design and validation challenges • Good command of English for reading technical documentation and communication • Proactive, eager to learn, and passionate about the latest electronics and AI hardware technologies 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

歡迎2026年畢業並正在找尋研發替代役的同學申請! 職位選擇: Direction 1: Physical Design Engineer Direction 2: ASIC Physical Design Engineer Direction 3: DFX Engineer Direction 4: CAD Tools Development Engineer Direction 5: Design Verification Engineer What you’ll be doing: Key Domains: • Physical and ASIC Design Implementation • Backend and Layout Optimization • Design-for-Excellence (DFX: Test, Manufacturability, Debug) • Development of CAD/EDA Automation Tools • Functional and Formal Design Verification What we need to see: • MS degree from EE/CS or related majors from a prestigious university. • Good knowledge in digital circuit design. • Experience in using Verilog HDL. • Experience in various EDA tools. • Fluent in English reading and writing. • Self-motivated, good team player. Ways to stand out from the crowd: • Proven ability to work independently as well as in a multi-disciplinary group environment • Good command of C/C++ or Verilog programming language. • Familiar with Perl/Python/Tcl/Shell scripting 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表：https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/CPU-Verification-Engineer--Up-to-Staff-Level_3063596 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://qualcomm.wd12.myworkdayjobs.com/External/job/Hsinchu-City-TWN/CPU-Verification-Engineer--Up-to-Staff-Level_3063596 【General Summary】 As a CPU Verification Engineer, you will be responsible for verifying design features across all aspects of CPU. 【Roles and Responsibilities】 • Develop deep understanding of CPU micro-architecture. • Work closely with design/verification teams within CPU to develop comprehensive test plan. • Use simulation and formal verification methodologies to execute test plans. • • Write checkers, assertions and develop stimulus. • Verify power intent through use of methodologies like UPF. • Work closely with system architects, software teams and Soc team to validate system use cases. • Work closely with emulation team to enable verification on emulators and FPGA platforms. • Debug and triage failures in simulation, emulation and/or Silicon. 【Minimum Qualifications】 • BS degree in CS/EE – with course work in computer architecture. • Experience with programming languages – C/C++ and scripting languages – Perl/Python. • Experience with hardware description languages – System Verilog/VHDL. • Implementation of assembly and C language embedded firmware • Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools 【Preferred Qualifications】 • Strong understanding of micro-processor architecture. • Strong understanding of power management, physical design concepts. • Experience in Silicon bring up and validation of CPU features. • Experience in debug of functional, power, performance and/or physical design issues in silicon. • Experience in CPU design and verification. • Experience in Test development for validation of CPU features on Silicon. • Experience in development of test vectors for tester bring up.

歡迎2026年畢業並正在找尋研發替代役的同學申請! We are seeking talented Firmware Engineers to join our team to work at the intersection of hardware and software, contributing to the core firmware that powers NVIDIA’s industry-leading GPUs and high-performance server products. In this role, you will design, develop, and optimize low-level software that enables reliable operation, high performance, and advanced features for both GPU and server platforms. These directions are: Direction 1: GPU Firmware Engineer Direction 2: Server Firmware Developer You’ll be doing: • Design, implement, and test embedded firmware for NVIDIA GPUs and server systems, enabling seamless hardware-software interaction. • Develop, maintain, and enhance bootloaders, device initialization code, and system management features. • Work closely with hardware, software, and systems teams to ensure robust bring-up and integration of new silicon and server platforms. • Diagnose, debug, and solve complex firmware and hardware-related issues across various development and production environments. • Drive innovation and optimization in areas such as power management, error handling, security, and performance monitoring for GPU and server hardware. • Contribute to documentation, compliance, and support for new product features and industry standards. Qualifications: • Master’s degree in Computer Engineering, Electrical Engineering, Computer Science, or related field. • Proficiency in C/C++ and embedded firmware development principles. • Understanding of computer architecture, hardware interfaces (I2C, SPI, PCIe), and real-time operating systems. • Experience with hardware bring-up, debugging tools, and low-level programming. • Strong analytical, troubleshooting, and communication skills. • Experience with server, GPU, or large-scale data center hardware is a plus. 應徵方式: 請提供以下資料： • 英文個人履歷 • 學士+碩士成績單 (中英文皆可) 提交申請: 請將上述資料投遞至104，符合資格者將會收到進一步的聯繫通知。

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

請務必投遞官網(12438): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer-ic-validator/44408/84710683632 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

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1.負責CPU設計的功能驗證，包括建立和維護驗證環境。 2.制定和實施約束隨機驗證策略，以確保CPU和相關外圍設計的功能正確性和性能。 3.運用覆蓋率驅動的方法來進行低功耗驗證，確保設計在各種功耗模式下的穩定性和效率。 4.實施形式化驗證和斷言基礎驗證，以提高設計的可靠性和降低錯誤率。 5.分析和處理驗證過程中出現的問題，與設計團隊緊密合作以進行問題定位和修正。 6.撰寫和維護相關的技術文檔，包括驗證計劃、測試案例和驗證報告。 7.跟踪最新的驗證技術和工具，不斷優化驗證流程和方法。

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446706469752 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446706469752 【The Potential Areas To Work Include】 • The main responsibility of this position is to do the performance analysis for world-class snapdragon CPU subsystem for mobile and portable computers. 【Minimum Qualifications】 • Master's, Electrical Engineering, Computer Engineering or Computer Science, emphasizing on computer architecture • Good knowledge on in-order/out-of-order CPU microarchitecture and architecture • Good knowledge on ARM bus protocol • Good knowledge on DDR subsystem • Good in C/C++ and scripting programming • Hands-on experience on performance analysis and validation works 【Preferred Qualifications】 • Experience in benchmark workload characterization and performance bottleneck analysis • Hands-on experience with performance verification on simulator or emulator • Familiar with ARMv8/v9 architecture • Knowledge of OS, firmware and software stacks • Familiar with GCC/LLVM compilation flow

【本職缺優先審核至高通官網投遞人選】請至高通官網上傳英文履歷表https://careers.qualcomm.com/careers/job/446706469791 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446706469791 【The Potential Areas To Work】 The main responsibility of this position is to do the performance verification for world-class custom CPU for mobile and portable computers. 【Roles and Responsibilities】 -Proficiency in one or more areas of CPU architecture: fetch, decode, branch prediction, renaming, execute units, SIMD, load/store, MMU, caches, retire, etc. -Verify performance feature between RTL and model, and have ability to troubleshooting -Work with design team and performance team to develop test case and validate new feature

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

1. Knowledgeable in power analysis and IR/EM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 2. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 3. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 4. Experienced in IO/IP planning, including bump/PAD placement and RDL routing is a plus. 5. Experienced in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre is a plus.

Job Overview: The role is to facilitate faster TAT for customer's cell level certification. As part of the modelling team, you will work on modelling enhancement for advanced process nodes. Work in a tight small group, growth opportunity for people with strong initiative. Job Responsibilities: - With support and help from Cadence Quantus team, you will gradually take full responsibility of customer's certification items. - You will collaborate and coordinate on modelling and engine enhancement to achieve certification goal. - You will also require cross-team collaboration, with Foundry Team, Techgen and xtor level modelling team. Job Qualifications: - Master in EE/CS/Physics/Math desired combined with 2 years of relevant experience , BS in similar area with 4 years of experience - Strong PhD with relevant research background can be considered. - Fluent in C++ coding and basic scripting - Good communication skills, independent, analytical skill, problem solver, team player Additional Skills/Preferences: Capacitance extraction, device modelling, interconnect modelling, electromagnetic simulation, static timing analysis, or place and routing experience welcomed.

1. VLSI Advance Technology Node (2nm and Below) Physical Design Implementation. 2. Comprehensive scope to touch, including chip floorplanning, a variety of design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3. Develop physical design flows/solutions on the cutting edge technology node.

The successful candidate will be a self-starter who likes to take responsibility and works best with little supervision. Likes to perform a variety of tasks and have the ability to handle multiple priorities and has previously performed in a similar position. This is a 'hands-on' role requiring a strong technical background and product development experience. Duties: • Identify technical issues, troubleshoot and resolve them by coordinating with R&D, Manufacturing and Field teams. • Participate in customer technical meetings and prepare training programs for internal subordinates. • Hardware validation of Networking, Storage, Server products against customer's infield issues, requirements and Mfg. issues during NPI or RMA. • System validation including DVT (Design Validation Trial), SPIT (Signal, Power, Integrity & Timing) environmental & regulatory approval. • Qualify alternative components for compatibility, cost effectiveness and benchmarking. • Support Manufacturing Engineering and Test Engineers on trouble shooting and resolving technical issues and root cause analysis. • Work with software teams to identify root cause of system failure. • Ability to install software such as Linux based Operating Systems, ONIE, BIOS, BMC, SES. • Proficient in using various test and measurement equipment including but not limited to Oscilloscope, Impedance analyzer, Power meter, Signal analyzer, Spectrum. Background: Candidates should have 8+ years' experience in either Network, Storage or Server products. Candidates should have the following essential qualifications and experience: • At least BEng. (Hons.) in Electronics or similar. • Strong electrical design and debug skills required. • Familiar with PCIe, NVMe, SAS, SATA, I2C, SPI, DDR buses. • SDRAM timing and integrity analysis for clocks, strobes, S&H, Power bounce, temp stability. • Hands-on design knowledge of latest peripheral chipsets for Gigabit Ethernet, SCSI, SATA, SAS, USB, Ethernet, & PCI cards etc. • High performance RISC / X86 CPUs and architecture including Intel, AMD, MRVL. • Proficient in using various test and measurement equipment including but not limited to Oscilloscope, Impedance analyzer, Power meter, Signal analyzer, Spectrum analyzer. • Qualify alternative components for compatibility, cost effectiveness and benchmarking. • System validation including DVT (Design Validation Trial), SPIT (Signal, Power, Integrity & Timing) environmental & regulatory approval. • Work with software teams to identify root cause of system failure. • Working knowledge of windows & Linux configuration, installation procedure, network configuration, driver configuration etc. • Working knowledge of Diag, ONIE, BIOS, BMC, Linux and Windows operating systems • Knowledge of the following would be desirable: - Experience of working in medium sized multidisciplinary development teams - Ethernet Switches, Server, Storage products - Orcad Schematics & Allegro PCB layout tools Personal Attributes: The successful candidate will be a self-motivated individual capable of working with a minimum level of supervision in a dynamic team environment. Good interpersonal skills. Be able to communicate effectively (both verbal and written) with members of other teams, departments and clients; a high degree of liaison is needed.

Job Description We are seeking a talented individual who will participate Virtuoso PDK (Process Design Kit ) development, quality and PDK applications related projects with leading foundry. This position will support Virtuoso PDK quality delivery, SKILL programming in task delivery, also provide PDK applications related support and interact with customers to overcome challenge in a fact-pace environment. Position Requirements: • MS degree in Electrical Engineering, Computer Engineering or similar areas. • Experience in analog design flow support or PDK delivery. • Knowledge and experience with analog design layout/simulation/digital/analog IC design flow, with layout domain knowledge would be a plus. • Experience in Linux shell environment and script programming, such as Perl and Tcl preferred. • Good communication skills in English. • Desire to learn, to take the challenge and to be a team player.

在宏成半導體，我們重視的是 態度、能力與學習意願，而不是任何單一的學歷或出身背景。過去我們曾與不同背景、不同專長的人才合作，他們都能在這裡找到發揮專長的舞台。 我們相信： 多元背景的人才 都能在這裡發揮價值。 重要的是 專注學習、願意承擔、樂於挑戰，而不是來自哪個學校。我們的研發方向屬於前瞻領域，團隊規模雖然不大，但每一位夥伴的努力都能 直接影響專案成果。因此，我們非常珍惜每一次面試機會，也希望雙方能在溝通時誠懇交流，確認彼此是否適合長期合作。 如果對公司的文化或制度有任何疑問，歡迎您在面試時直接提出，我們會誠實回應，並期待找到 真正志同道合 的夥伴，一起實現願景。 AI 邊緣運算 IC / IP 設計 RTL Coding / Functional Verification FPGA 驗證與系統整合

 Display port IP architecture definition  RTL design and functional verification  FPGA verification  Synthesis and static timing analysis