「Staff/Sr. CPLD/FPGA Firmware Engineer (Server)」的相似工作

我們正在尋找一位資深人員，帶領FPGA專案開發，包含主機板時序控制、客戶FPGA專案需求開發設計，及FPGA實作上必要時需與軟硬體研發團隊成員進行協作。 工作內容： 1. 數位邏輯設計並熟悉RTL Coding架構。 2. 熟悉並使用Altera Quartus或Xilinx Vivado開發FPGA系統。 3. 熟悉主機板CPU power sequence control。 4. 熟悉影像方面的高速介面(SDI/HDMI)、DDR高速介面、PCIe、I2C、UART、SPI等介面應用。 5. SoC FPGA系統整合。 6. FPGA IP 整合及驅動程式開發。

Overview We are seeking a highly skilled FPGA Engineer to architect and implement high-performance digital logic for next-generation camera platforms. This role is pivotal in enabling real-time video processing and efficient sensor integration. Key Responsibilities Design & Implement Camera Interfaces: Develop FPGA logic to handle high-speed camera data streams (e.g., MIPI, LVDS, CSI). Real-Time Image Processing: Integrate or design FPGA IP cores for image signal processing, filtering, and feature extraction. Sensor Synchronization: Ensure precise timing between multiple camera modules and other sensor inputs. Latency Optimization: Optimize FPGA architectures for low-latency video capture and data throughput. Verification & Testing: Create simulation testbenches and perform hardware-in-the-loop testing for camera pipelines. Collaboration: Work closely with camera hardware and system integration teams to define requirements and validate performance.

1.Work with Hardware, BIOS ,BMC, and Firmware team for CPLD design, validation, and maintenance 2.Develop Server production power on sequence control logic by CPLD / FPGA 3.Implement new technology and design concept in CPLD / FPGA Design test plan, development specification, and issue tracking.

1. 主FPGA與CPLD專案開發與維護 2. 熟RTL coding, 具Xilinx ISE/Vivado或Altera Quartus II專案設計經驗 3. 能與軟,韌,硬體等相關部門co-work 4. 具Xilinx PCIe 與 MIG DDR3/4系統整合經驗者佳

1. 熟Verilog及C/C++語言設計。 2. 規劃執行產品韌體之撰寫。 3. 執行、協助或配合韌體新技術之研發、導入。 4. 執行產品韌體測試。

The Team and Role: The Embedded SW Test team’s mission is to strengthen the firmware validation process and fully automate the test procedures. We develop truly innovative test instruments and tools to achieve this goal. The FPGA Firmware Developer /Test Engineer is responsible for designing, implementing and testing FPGA firmware used for test automation. Your Contribution: Be Yourself. Be Open. Stay Hungry and Humble. Collaborate. Challenge. Decide and just Do. These are the behaviors you’ll need for success at Logitech. In this role you will: • Participate in the development of a test automation framework • Leverage your technical hardware and software skills to design & implement the testing infrastructure • Evaluate and develop new FPGA modules to automate the integration test suites for our next generation devices • Develop, run and maintain automated scripts to prove product conformity regarding component specification • Improve processes or propose improvement where’s applicable

【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力

ᴘᴜʀᴘᴏsᴇ ᴏғ ᴛʜɪs ᴘᴏsɪᴛɪᴏɴ 運用 FPGA 技術打造高效能與高可靠性的工業網路產品，支援全球製造、能源與交通等關鍵產業的數位化轉型。 ᴍᴀᴊᴏʀ ᴀʀᴇᴀs ᴏғ ʀᴇsᴘᴏɴsɪʙɪʟɪᴛʏ 1. 負責 FPGA 邏輯設計、Simulation、驗證與 Debug。 2. 與 EE、FW、PM 等跨部門協作，確保系統整合穩定，及時回應客戶需求。 3. 維護既有產品並持續改善品質與效能。 4. 撰寫設計與測試文件，遵循並優化開發流程。 5. 協助新產品平台架構設計與技術評估。

(1) FPGA軟硬體開發 (2) Verilog程式開發 (3) 軟硬體除錯

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)

1. Work closely with Hardware, BIOS ,BMC, and Firmware team for CPLD / FPGA design, validation, and maintenance. 2. Develop multiple bus protocols including I2C / power sequence / SPI / LPC / SGPIO / I2C switch/ UART / PWM / eSPI on Server / Storage product by CPLD/FPGA. 3. The test issue analysis and track and troubleshoot of the project.

A. 負責高階投影機FPGA開發 B. 承接 FPGA (XILINX/ALTERA) 設計 C. 數位電路設計、驗證與模擬 D. 影像系統或數位影像處理演算法設計與實現

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

產品領域: 影像, CPO及衛星光通訊產品使用之 FPGA。 工作內容: 1. 熟練使用Verilog及VHDL 2. 熟悉Combine/Sequential Logic、FSM、pipeline、clock domain crossing (CDC)、reset strategy 等應用 3. 自動化設備嵌入式系統開發 4. 研發設計FPGA-Based Video/Camera 應用 5. 熟悉FPGA系統開發、RTL Coding、Altera Quartus II或Xilinx Vivado 6. 協助驗證FPGA電路(Schematic) 7. 具備基礎MS Windows Programming能力者佳 8. 熟悉I2C、UART、I2S 等protocol 者佳

The successful candidate will work with team members and apply his/her design techniques to work on different phases of complex logic design for ASIC/SOC project. The role will include working on the following tasks from time to time: HDL coding, documentation, RTL quality check, cooperate with back-end engineer etc. 【Key Responsibilities】 - Responsible for front-end digital logic design in ASIC/SOC projects. - Perform HDL coding (Verilog/SystemVerilog). - Prepare and maintain design documentation (specifications and design documents). - Conduct RTL quality checks (Lint, CDC, power analysis, etc.). - Collaborate with Backend/Physical Design engineers to achieve timing closure. 【Core Requirements】 - Education/Experience: Master’s degree with ≥ 2 years, or Bachelor’s degree with ≥ 3 years of digital ASIC/SOC design experience. - RTL Design: Proficient in RTL coding using Verilog/SystemVerilog or VHDL. - TO / Front-End Flow: Familiar with front-end design flow, including synthesis, Lint, CDC, and STA. - EDA Tools: Experience with tools such as Lint, CDC check, and PrimeTime PX (power analysis). - Documentation: Ability to write design specifications and technical documents. - Collaboration: Work closely with the Design Verification (DV) team on IP verification. 【Preferred Qualifications】 - Familiarity with CPU architectures (x86/ARM/8051). - Knowledge of AMBA bus protocols (AXI/AHB/APB). - Understanding of PCIe protocol.digital IP/SOC design verification.

Job Description: Microchip’s Wireless Solutions Group is seeking a FPGA engineer to support SOC development for our next generation, mixed signal, wireless products. The role will focus on the areas of RTL design, FPGA synthesis and FPGA system bring-up, debug and validation. It will require a proactive candidate with a proven record of success in cross functional and cross site team environments. Key Responsibilities: • Collaborate with the design team to develop and optimize the RTL for FPGA , ensuring its efficiency and functionality. • Conduct FPGA synthesis using industry-standard tools to transform RTL code into a target FPGA device. • Assist in the initial bring-up of the FPGA system, ensuring proper functionality and identifying and resolving any issues that may arise. • Perform through testing and validation of the SOC design, both at the RTL level and in the FPGA implementation, and resolve any bugs or issues that are discovered. • Collaborate closely with the FW (Firmware), Validation, and RF teams to successfully carry out FPGA system bring-up, debug, and validation activities.

震昇科技因應公司業務擴大規模，增設職務。 希望尋找擁有共同理念的人才一同成長打拼。 到職後職稱：研發專案經理 【職務內容】 1. 理解團隊成員能量並整合、分配部門工作 2. 管控各專案時程進度，確保符合時程及規範 3. 定期彙報，並提出改善建議 4. 跨部門溝通協調 【需求特質】 1. 相關年資5年以上 2. 具備管理經驗 (人數3人以上) 3. 具備自主管理能力，有獨立作業及思考能力 4. 具備團隊精神，內部溝通整合能力 5. 溝通表達能力良好 【需求技能】 1. 具有分析類比/數位電路能力，有使用ORCAD 或 AD 電路圖繪製經驗。 2. 具備Windows以及Linux的安裝/配置能力，有使用Real Time OS的經驗更佳。 3. 熟悉 PCIe，HDMI，USB2.0/USB3.0，Ethernet等等PC常用Protocol，有軍用Protocol(比如1553，VME，VPX等等)使用 經驗更佳。 4. 熟悉C/C++ 以上經驗更佳。 5. 熟悉FPGA開發流程，具有Verilog或VHDL開發經驗更佳。 ※請求職者利用104平台投遞履歷及聯繫，勿於官網留言或撥打公司電話，謝謝※

1.具FPGA平台開發相關經驗 2.熟Verilog 3.熟顯示器TCON/Driver驅動原理者佳 4.能獨立建立FPGA開發環境平台 5.有數位邏輯IC開發經驗者佳

我們專注於打造次世代電路模擬專用硬體加速器，誠徵數位IC設計師，加入我們的行列，透過數位電路設計與驗證實力，推動電路模擬的極致效能與可靠性。 你將負責： ▪️ 設計電力分析專用晶片架構及系統 ▪️ RTL設計與功能驗證，確保系統正確性與效能表現 ▪️ 參與SoC數位區塊的功能設計、整合與驗證 ▪️ 進行綜合、時序分析與低功耗設計優化 我們期待你具備： ▪️ 電子/電機工程學士以上學歷 ▪️ 精通Verilog/SystemVerilog與RTL設計流程 ▪️ 熟悉綜合與時序分析方法 ▪️ 具備DSP演算法硬體實現經驗 ▪️ 理解低功耗設計技術與實務 專業工具： ▪️ Synopsys Design Compiler ▪️ Cadence Genus ▪️ Mentor Graphics 加分條件： ▪️ 具備完整SoC設計專案經驗 ▪️ 熟悉UVM或其他驗證方法學 ▪️ 有28nm以下先進製程設計或量產經驗 ▪️ 具備電力電子或電源管理電路相關背景 如果你熱愛透過數位IC設計挑戰能源晶片的極限，歡迎加入我們，打造更智慧的硬體未來！

1.電子電路設計開發。 2.自動測試設備設計開發。 3.半導體相關設備之維修開發。 4.航太電子設備之維修開發。 5.通信電子設備維修開發。