「IR Signoff/Codesign 工程師」的相似工作

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

1. ARM CPU design physical implementation 2. ARM CPU power and timing sign off 3. Physical design flow enhancement for high-speed CPU

1.有analog/mixmode ic layout 經驗 2.熟悉laker,virtuoso,calibre 3.有整合能力可以獨立floor plan或有N12/N10/N6製程經驗尤佳 4.需穩定且積極主動與配合度高

1.CIS/3DIC/HBM & RDL package layout. (follow customer design) 2.Daisy chain design 3.Wafer 排版評估及圖面製作 4.光罩排版設計 5.Job file資料提供及其它生產相關圖面製作.(POD drawing, Mask drawing, Unit drawing Other Job Function 1.Check Mask Design SOP (L-EDIT ). 2.Design review meeting. 3.Review and maintain for relevant document ＊實際薪資依學歷、科系、相關工作經驗、專業證照、特殊專長與語言能力綜合核敘。 ＊資深人員薪資另議。

1. Analog IC layout 2. Channel or chip integrate

1.Chip level IR drop 分析 2.Chip power estimation/calculation 3.IR drop flow 建構 4.IR drop tool 維護 5.撰寫程式

Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Chip Planning • Project Schedule / Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Top Level connections • Signal matching / sensitive nets shielding technique • Chip power / ground planning • Integration of Analog top with Auto-Placement-Routing • Pad / ESD rule and routing / connection • Database DRC & LVS verifications on either DIVA or Dracula basis • Chip Tape-out in accordance with company’s Tape-out Procedure • Positive Attitude Qualifications: • 3+ years Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable

【產品範疇】 Mobile/TCON - LCD display driver、OLED display driver Tablet - LCD display driver TV/NB -LCD display driver TCON 產品 【工作內容】 1.DRC/LVS Command file 撰寫&Maintain 2.Laker TF/UDD/PCELL 撰寫 3.PERC rule & 程式的開發 4.Analog design flow development 5.Shell/SKILL/TCL/Python 程式開發 6.新製程廠內的PDK development 7.In house Utility 開發 8.AI 輔助工具的開發與評估

1. SoC top-level (Analog+Digital) Integration 2. Design block integration, synthesis, verification

RTL design/Verilog behavior model development APR flow support CAD/CAE internal flow/script maintenance

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責基礎元件 IP（Foundation IP）開發相關的Memory Designer RD職缺。 【將負責的工作內容】 1. SRAM circuit design 2. Memory compiler development 3. Memory instances characterization 4. Supervision of layout implementation 【條件與特質】 1. Be familiar with memory circuit design : full-custom, read/write operation scheme, sense-Amplifier analysis, RAM cell analysis, monte carlo simulation, read/write margin check. 2. Be familiar with tool : linux, spice, finesim, virtuoso, laker. 3. Experience with FinFET process or high sigma design will be better. 4. 5年以上相關經驗 5. 電機電子相關學系碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

如欲投遞履歷,請上Amkor官網 https://careers.amkor.com.tw/ Job responsibilities for this position includes physical design/layout in FC and Wirebond substrate based technology, package selection, and design rule implementation. This involves optimizing system co-design of IC and Package, IC floor-planning, ball array optimization to meet signal & power integrity, assembly, and thermal constraints.

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

1. SAR ADC / Current steering DAC/ SDM ADC/ DAC related 2. Analog Baseband related 3. 據有類比整合相關經驗佳

1. Backend design tool and flow support - Innovus/ Calibre flow support 2. Timing / Power / SI convergence flow for backend flow 3. IR / EM flow tool usage support *備註：此職缺非研發替代役*

1. 建置與強化聯詠數位設計流程 2. 評估與導入前瞻數位設計流程 3. IC數位設計流程自動化程式開發 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠

1.IC Implementation & Verification - including floorplan, CTS, STA, IR-drop analysis, DRC&LVS. 2.Familiar with EDA tools including ICC , Encounter 3.TCL/perl script programming. 4.Low power flow is preferred.

1.機構圖/電路圖剖析轉檔 2.依電氣/安規/製程/客戶規範進行零件擺放/銅箔線路規劃設計 3.PCB排版圖繪製 4.工程圖面轉置發行 4.PCB料號申請 5.PCB文件上傳系統

Digital IC design engineer - Familiar with Verilog RTL coding - Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation) - Will be working on high speed Serdes IPs - Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus

1. Proficient in fundamental circuit structures (e.g., standard cells, IO), with the ability to simulate basic circuits using Hspice or Spectre. 2. Experienced in IO/IP planning, including bump/PAD placement and RDL routing. 3. Familiar with the integrated circuit (IC) design flow, capable of performing design, optimization, and verification using tools such as ICC2 or INNOVUS. 4. Knowledgeable in power analysis and IREM methodologies, with hands-on experience using Ptpx, Redhawk, or Voltus for power and IREM evaluation. 5. Experience in developing automation scripts using Python, Perl, TCL, or Shell is a strong plus. 6. Experience in layout design using Virtuoso or Laker is a plus. 7. Knowledge of one or more of the following domains is preferred: semiconductor processes, ESD protection, digital and analog circuit design, signal integrity, power integrity, timing analysis, physical verification, thermal analysis, and mechanical analysis.