「PE-產品工程師」的相似工作

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

1.記憶體晶片CP/FT測試程式開發維護(Advantest ) 2.新產品開發驗證 3.測試程式開發與良率、穩定性改善 4.量產產品測試良率分析處理

1. MP Management (50%) 1-1. Yield improvement and cost reduction activities. 1-2. Abnormal Lot disposition, diagnose problems and offering a solution with the balance of efficiency and quality control. 1-3. Foundries/OSATs capacity expansion planning and executing. 2. NPI(New product introduction) Management (35%) 2-1. Coordinate new Tape-out schedule and release to MP activities. 2-2. Perform and consolidate product reliability qualification. 3. Cross-department support, consolidate specific activities. (10%) 4. Advanced foundry process technology survey and implementation. (5%)

1. Foundry Tapeout Account 申請。 2. Foundry 製程能力評估和Tapeout 與良率提升。 負責評估Foundry製程能力，Tapeout 作業，持續推動製程優化，進而提升產品良率。 3. 跨單位工程問題協調 代表公司與客戶、Foundry、封裝廠及光罩公司協同解決各項工程相關問題。 4. 產品流程管理與分析 負責從Tape Out、Mask Job Review到產品量產的全流程管理，並進行與協力商處理ESD與Latch Up分析。 5. 封裝評估與導入,與測試數據分析. 6. HTOL QUAL 和 Package QUAL可靠度測試,與RMA分析. 7. 異常問題查證與製程改善 當產品異常發生時，運用EFA/PFA找出低良率原因，並與RD、Fab及Assembly部門協作解決，持續推動製程改善。 8. 熟悉Packaging(WLCSP、wire bond、Molding...)與Testing(CP、FT...)各階段等，知道如何與Test Engineer/外包討論ATE平台、測試coverage、bin split 等議題 9. PDK及相關文件管控 主導PDK及相關文件的申請作業，並與PM/RD團隊密切合作，嚴格控管文件版本，確保資料一致性與最新狀態。 10. 主管交辦事項.

1. To improve device yield &CIP in order to meet customer request and customer service. 2. Identify and solve process and device problems. 3. Support for customer visit and audit.

1.協助客戶與原廠產品對接 2.協助原廠開發新材料應用 3.協調公司內部資源及客戶需求 4.開發潛在客戶，拓展市場 5.客戶拜訪，維繫客戶關係

1. 專案管理 / 執行 2. 需出差(北中南) 3. 繪圖:3視圖經驗

1. 熟悉FAB 8”wafer Driver、Power IC/MOS/CSP Module等產品製程相關經驗 2. 具備量產WAT/CP/FT driver與MOS產品良率分析與異常處置 3. 熟悉電性分析、FA失效分析工具、Yield Hub 等良率分析軟體操作經驗 4. 良率改進、供應商管理 5. 協助QA客訴異常分析/驗證與root cause問題查找分析處置經驗 6. 其他主管交辦事項 【工作待遇依工作經歷敘薪】

1.擔任產品負責人 2.DFM技轉 3.召開改機會議、新產品產前產後會議 4.撰寫技術文件、生產流程文件 5.首件核對、製成優化

工作概覽： 參與CMOS平台製程開發、元件設計與電性優化，支持新產品導入、製程整合與技術創新，為特殊應用產品提供完整的製程與元件解決方案。 主要職責： • 負責0.35um CMOS製程模組與整合開發。 • 參與元件(如MOS、HVLDMOS、電容、電阻等)之設計與TCAD模擬驗證。 • 建立元件模型(SPICE/LPE) 與電性分析，協助PDK開發。 • 協同設計團隊進行元件規格定義與效能驗證。 • 支援新產品導入、製程異常分析與良率改善。 資格條件: • 熟悉0.35um CMOS製程平台。 • 具元件設計、TCAD模擬或SPICE建模經驗者尤佳。 • 具備製程整合、電性量測與數據分析能力。

1. 電路圖繪製/閱讀、維修，硬體除錯，良率提升。 (Altium Designer/cadence spb allegro) 2. 熟悉烙鐵操作及示波器&電表等儀器操作。 3. 元器件倉儲控管/收發配件運送等。 4. 負責工廠測試環境架設。 5. 負責現場生產線不良品維修及故障排除。 6. 執行PCB焊接、檢修、維修及更換零組件或線路調整。 7. 負責測試配件問題之研究、改善與處理。 8. 具備文書處理技能。 9. 配合專案，國內封測廠出差。(需有汽車) 10. 完成主管交辦事項，配合加班。 11.需要自備汽車。

1.PCB測試板工程變更/Debug/Maintain(需要焊接) 2.PCB測試板上機驗証(需PCB維修相關經驗，維修過LB、PC、BIB尤佳) 3.面對客戶、與客戶溝通工程內容

Focus areas: Delivery, cycle time, and line yield. 1. Handover from RD and maintain mass production product 2. Line Yield enhancement and monitor 3. 有在MOS CP/FT廠，或BGBM 廠，孰悉運作等相關經驗者尤佳。 4. 擴產驗證評估 5. Back-end process monitor and maintain

1. 國內出差處理客訴問題 2. 國內出差解決客戶的產品安裝問題 3. 維修不良產品 4. 主管交辦事項

【產品線描述】 Smart TV Solutions：提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions：提供智能手機、智能電視、電競螢幕、AI Server等產品各種ASIC(包含CoWoS/ChipLet平台)解決方案 【工作說明】 先進封裝 Package/substrate 設計工程師，主要規畫 SoC IC 封裝，整合開發驗証的 EVB 設計。 1. 負責IC floor plan, IO pin mux 及 PAD location規劃。 2. 負責 ball map 規畫, Substrate基板設計佈局。 3. 電路板開發 (EVB) 設計與除錯 【必要條件】 1. 須熟悉OrCAD, PADS and Cadence Allegro 等應用軟體。 2. 具備PCB/Substrate design及傳輸線理論等相關知識。 3. 具備電子電路，Power 架構設計， SI/PI概念。 4. 具一年以上BGA封裝設計, 熟悉各種類型之封裝及基板設計, 有 CoWoS 封裝設計經驗尤佳。 5 積極、跨部門溝通協調能力、有責任感 。

1. 新產品開發驗證以及量產條件的決定 2. 量產品管理及良率改善，量產品產品特性分析，客退品分析報告 3. 新技術開發平台開發

1. LV/HV ESD/Latch-up device/rule development 2. Foundry in customer's ESD/EOS/Latch-up problem consult 3. Foundry out之MCU, Speech, Super I/O, Power IC等自有產品線之ESD/ EOS /Latch-up protection design

Please apply this role through https://careers.synopsys.com/job/hsinchu/r-and-d-engineering-sr-staff-engineer/44408/84900058096 Synopsys is looking for motivated Product Engineer to help design, develop and test state of the art Static Timing, Characterization and Library modelling tools. The primary focus of the Product Engineer is closely working with R&D team, to influence technologies/solution roadmaps and provide R&D team with accurate input from Field AEs, helping them focus on the most critical design challenges and help define solutions to critical problems. The engineer will work closely with Field AEs, ensuring overall consistency of end-to-end design and analysis flow to meet customer needs. The engineer will also work with Sales and Marketing teams to find and develop new markets, drive new tool evaluations and help customers with the adoption and continuous usage of Static Timing, Characterization and Library Modelling, thus enabling Chip Design customers achieve best Timing, Power and Characterization Goals. Synopsys’ existing and forthcoming tools offer an advanced transistor-level static timing characterization and library modelling solution that addresses the existing and emerging challenges in custom and memory design. They offer predictability and improved productivity to designers. Their concurrent timing, SI features and advanced variation aware analysis enables designers to accurately and quickly identify design issues early-on and avoid expensive late-finding of problems in silicon. Main responsibilities: • Drive new products and new product features that exceed customer needs. • Work with RnD to enable timely implementation of new products and features, and important bug fixes. • Provide consultation to prospective users and/or product capability assessment and validation. • Provide tool trainings to customers and Field AEs. • Provides technical expertise to sales staff through sales presentations and product demonstrations. • Assists the sales staff in assessing potential application of company products to meet customer needs and preparing detailed product specifications for the development and implementation of customer applications/solutions. Requirements: We are looking for an innovative, motivated, and dependable person, with at least BS degree and 8+ years of recent hands-on experience including: · Exceptional expertise in transistor-level analysis and debug circuit level issues for SRAM, RF, ROM memories and Standard Cells. · Good exposure to static timing concepts and CMOS engineering fundamentals. · Good knowledge of TCL and or other scripting languages. · Very good communication, social and leadership skills. Plus: · NanoTime or PrimeLib experience highly desirable.

MaxLinear is seeking a Staff Product Engineer to join our growing team in Taiwan. In this role, you will be responsible and focus on the following: • Full product life cycle ownership • Co-define ATE test, characterization, qualification, manufacturing plans • Co-define test spec and control limit • Co-work on CRAs analysis • COGS analysis and reduction • Data and yield analysis and improvement • Co-work with internal cross-functional teams and OSATs

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