「PE-產品工程師」的相似工作

我們正在尋找一位經驗豐富、對半導體元件物理有深入了解的SPICE元件工程師加入我們的團隊。您將負責開發、驗證及維護用於積體電路設計的SPICE模型，確保模型的高精準度與可靠性。 【職務內容】 SPICE元件模型開發與驗證： 1.負責開發各類半導體元件(如MOSFET/HV MOS/BJT/Diode/Res & Cap等)SPICE模型。 2.執行模型參數萃取與最佳化，確保模型數據與量測數據高度吻合。 3.開發設計模型驗證Pattern，包括DC、AC、Qg/Qd、Qrr及雜訊特性驗證。 4.協同製程開發團隊，確保模型能準確反映製程變化。 5.模型維護與支援電路設計： 5-1)定期更新與維護現有SPICE模型庫，以支援新製程節點/平台及設計需求。 5-2)為設計工程師提供SPICE模型相關技術支援，協助解決設計中的模型與模擬問題。 5-3)透過與實際IC行為的驗證與分析，完善元件模型架構與建立精準模擬設定流程。 5-4)對IC量測數據進行深入分析，以識別模型局限性並提出改進方案。 5-5)建立並維護模型參數萃取與驗證的自動化流程。

1. 專案管理 / 執行 2. 需出差(北中南) 3. 繪圖:3視圖經驗

1. LV/HV ESD/Latch-up device/rule development 2. Foundry in customer's ESD/EOS/Latch-up problem consult 3. Foundry out之MCU, Speech, Super I/O, Power IC等自有產品線之ESD/ EOS /Latch-up protection design

1. Foundry Tapeout Account 申請。 2. Foundry 製程能力評估和Tapeout 與良率提升。 負責評估Foundry製程能力，Tapeout 作業，持續推動製程優化，進而提升產品良率。 3. 跨單位工程問題協調 代表公司與客戶、Foundry、封裝廠及光罩公司協同解決各項工程相關問題。 4. 產品流程管理與分析 負責從Tape Out、Mask Job Review到產品量產的全流程管理，並進行與協力商處理ESD與Latch Up分析。 5. 封裝評估與導入,與測試數據分析. 6. HTOL QUAL 和 Package QUAL可靠度測試,與RMA分析. 7. 異常問題查證與製程改善 當產品異常發生時，運用EFA/PFA找出低良率原因，並與RD、Fab及Assembly部門協作解決，持續推動製程改善。 8. 熟悉Packaging(WLCSP、wire bond、Molding...)與Testing(CP、FT...)各階段等，知道如何與Test Engineer/外包討論ATE平台、測試coverage、bin split 等議題 9. PDK及相關文件管控 主導PDK及相關文件的申請作業，並與PM/RD團隊密切合作，嚴格控管文件版本，確保資料一致性與最新狀態。 10. 主管交辦事項.

1.了解SiP， CPO或光電產品結構設計&驗證。 2.孰悉光電產品製程開發設計& 改善。 3.異常分析&解決對策。 4.有Zemax相關實作經驗尤佳。

1. To improve device yield &CIP in order to meet customer request and customer service. 2. Identify and solve process and device problems. 3. Support for customer visit and audit.

IC及System ESD防護設計

1. 電路圖繪製/閱讀、維修，硬體除錯，良率提升。 (Altium Designer/cadence spb allegro) 2. 熟悉烙鐵操作及示波器&電表等儀器操作。 3. 元器件倉儲控管/收發配件運送等。 4. 負責工廠測試環境架設。 5. 負責現場生產線不良品維修及故障排除。 6. 執行PCB焊接、檢修、維修及更換零組件或線路調整。 7. 負責測試配件問題之研究、改善與處理。 8. 具備文書處理技能。 9. 配合專案，國內封測廠出差。(需有汽車) 10. 完成主管交辦事項，配合加班。 11.需要自備汽車。

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

【工作內容】 1. Technical support for spec./manufacture/quality of design-in, driving root cause of CCR. 2. Internal collaboration with CPD/ME/QE/PM. 3. Internal project development PDK and Daisy chain for interposer. 4. Build relationship with ASIC vendor/substrate/package OSAT. 【工作經歷】 1、通信/電子/半導體相關專業。 2、熟悉IC製程(front-end)、2.5D封裝、測試(back-end)並具製程整合、改善相關經驗。 3、產品應用技術撰稿 (Documentation): Datasheet、Application note 、Technical report 4、客戶服務(Design in and CCR)，技術問題回覆，根因分析報告。 5、具OSAT合作開發及應用推廣經驗。 6、具備專案開發、進度管理能力。

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1.PCB測試板工程變更/Debug/Maintain(需要焊接) 2.PCB測試板上機驗証(需PCB維修相關經驗，維修過LB、PC、BIB尤佳) 3.面對客戶、與客戶溝通工程內容

1.擔任產品負責人 2.DFM技轉 3.召開改機會議、新產品產前產後會議 4.撰寫技術文件、生產流程文件 5.首件核對、製成優化

MaxLinear is seeking a Staff Product Engineer to join our growing team in Taiwan. In this role, you will be responsible and focus on the following: • Full product life cycle ownership • Co-define ATE test, characterization, qualification, manufacturing plans • Co-define test spec and control limit • Co-work on CRAs analysis • COGS analysis and reduction • Data and yield analysis and improvement • Co-work with internal cross-functional teams and OSATs

1.客訴分析處理與協助廠內改善跟催 2.處理客戶生產加工上所遭遇的問題, 解決並提供協助與對策 3.協助集團公司處理產品可靠度驗證與客訴問題 4.產品可靠度驗證暨產品可靠度監控 5.協助改善可靠度作業流程 6.HTOL/bHAST/PTC burn-in board規劃 7.ISO文件/表單制定及修改 8.其它主管交辦事項

工作內容: 1. 新產品測試評估(DFT) 2. 新產品測試軟/硬體開發與驗證 3. 協助驗證產品規格、封裝、可靠度 4. 新產品測試量產導入 5. 協助改善產品良率及優化測試時間 6. 協助測試量產異常處理 7. 能配合加班，及配合公司需求調整工作內容與職務

【Position Overview】 We are seeking a highly motivated and experienced Foundry Engineer to join our team. In this critical role, you will be responsible for driving product yield, performance, and reliability by collaborating closely with internal teams and external silicon foundries. You will identify the root cause of process, device, and defect-related issues, propose and execute improvement plans, and ensure to meet our yield KPIs and product timelines. This position requires a strong technical background in semiconductor manufacturing, excellent problem-solving skills, and the ability to work effectively in a collaborative environment. 【Responsibilities】 1. Lead foundry engineering activities to drive product yield, performance, and reliability/quality to fulfill product needs. 2. Collaborate with cross-functional teams to ensure timely new product introduction and proactively address potential issues. 3. Develop and execute yield improvement plans by collaborating with internal teams or external foundries. 4. Ensure high production quality control through in-depth analysis, inline and WAT monitoring, and investigation of customer returns. 5. Manage projects effectively to meet deadlines and achieve objectives.

- Own backend external manufacturing NPI from conceptualization, development, qualification to production launch with a focus on wafer-level packaging (WLP) and post-fab solutions - Functional Leadership for NPI to deliver PLM requirements for new product commercialization and to co-work with cross functional team (comprising both internal and external stakeholders) to achieve on-time market release - Drive DFM, technology & manufacturability readiness for new product/ package development, effective POR freeze for new product introduction - Partner with OSATs to deliver assembly readiness for new product qualification. Key activities include BOM & process setup, risk analysis & mitigation, process characterization, lookahead assessment, qualification and CAB preparation leading to first part release - Manage production ramp: lead production safe launch, provide technical support to resolve ramp issues, develop CIP, set production baseline for transition into HVM - Collaborate with internal & external partners for technology pathfinding, package roadmap as well as design rules/ guideline development - Adoption of data analytics and data-driven approach to problem solving and decision making - Establish Best Known Methods (BKM) and Best-in-Class practices for new package platform and fan-out to production - Participate in quality and process readiness audit to achieve production site readiness - Co-work with operations to drive continuous yield improvement for evolving challenges - Subject Matter Expert to address arising package and assembly challenges - Experienced candidate(s) will be considered for lead role to manage team activities

1.作為應對客戶的品質窗口，負責客訴異常處理與回覆 2.處理 RMA / Return 品分析與報告撰寫（EFA, PFA） 3.負責客戶品質稽核應對與資料準備 4.撰寫與追蹤8D報告、根因分析（RCA）及矯正預防措施（CAPA） 5.跨部門溝通，推動品質改善方案

製程整合/元件開發