「數位IC設計工程師IV-台北」的相似工作

1. 光通訊產品相關高速介面數位設計 (112G PAM4 SerDes) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL) 3. 具有高速介面, 低功耗, 以及D/A混合電路設計經驗者尤佳

1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)

- Experience with memory controllers (e.g. DDR DRAM, eMMC and other flash, etc.) - Experience in CPU or various buses (AXI, etc) - Good verilog writing skills - Willingness to work with a variety of tasks

工作內容： 1. 數位IC電路設計，模擬驗證及下線 2. 數位IC設計流程，包括Linting、Synthesis、DFT、STA...等. 3. FPGA硬體設計 相關應用: 1. 電源管理IC數位電路設計 2. Interface protocol design - I2C、PMBus、SPMI、I3C...etc. 3. Power management state / sequence / fault / charger control...etc. NVM (eFuse/OTP/MTP) controller

Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA

請在您投遞履歷時同時回答您以下問題! 1: 你為什麼想加入一家早期AI邊緣運算公司？ 2: 假如這家公司未來三年內無法保證升遷與高薪，你仍願意投入嗎？為什麼？ 3: 你是否願意融資前薪資略低，但享有融資後股權參與機會？ 4: 我們這邊沒有華麗的資源，也沒有很多人手，甚至連教育訓練也不完備，你來這裡就是要跟我一起摸黑開路。你願意嗎？ AI 邊緣運算 IC / IP 設計 RTL Coding / Functional Verification FPGA 驗證與系統整合

1. 負責數位電路設計和RTL 和IP design, 模擬和驗證. 2. 與類比設計和系統設計, 佈局設計工程師溝通和協作. 3. 實現FPGA emulation和測試平台開發. 4. 協助量產測試程序的開發. 5. 規格書和Design Document的撰寫. 6. 工作地點在台北內湖

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

Key responsibilities: • Perform IC design of FTDI products • Perform Verilog RTL design to meet product specifications and requirements • Perform front-end verification using UVM methodology • Work with Systems and Software engineers on FPGA verification • Perform Logic Synthesis, Static Timing Analysis • Lead DFT related activities - Scan Insertion, ATPG, Pattern Validation • Work with Physical designer to achieve timing closure • Work with test team in debugging production test issues • Help debug & correct any functional issues found in taped-out devices • Participate in design reviews, support ISO processes and documentation Additional responsibilities: a) Any reasonable task assigned by management and deemed to be within the individuals’ capabilities to ensure smooth running of the business. b) As this is an evolving business, ongoing change is an integral part of the position. Management will liaise with the individual on any fundamental change to work practices. The individual is required to embrace and adopt any change to working practices. Knowledge and skill requirements: • Degree/Master in Electrical/Electronic Engineering • 5 years or above experience in the area of digital IC design • Working experience from design to tape-out are essential • Experience in Verilog HDL and VHDL RTL design, OVM/UVM verification methodology , Logic Synthesis, DFT, ATPG, Timing Closure • Experience in using EDA tools from Cadence, Synopsys • Knowledge and working experience in one or more of the following: o Digital and mixed-signal design o USB interface products o Knowledge in connectivity technology such as USB, UART, SPI, I2C o Project Management Working conditions:  Working conditions are normal for an office environment.  Work requires willingness to work a flexible schedule.

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 工作內容： 1.負責 IP 介面控制與時序邏輯設計，確保模組穩定性與資料正確傳遞。 2.參與 SoC 上層模組連線設計與系統整合工作。 3.使用 Verilog 撰寫 RTL，並執行功能模擬與波形分析。 4.使用 FPGA 進行模組與系統功能驗證，支援原型測試。 5.執行 ASIC 設計流程，包括邏輯綜合（Synthesis）、DFT、clock domain crossing、timing closure 等。 6.配合後段（backend）設計工程師完成實體整合與 Tape-out 作業。 7.參與加解密 IP（AES、SHA、RSA、TRNG、PUF、PQC 等）之數位邏輯設計與驗證整合。 8.使用 UVM 或相關驗證方法學開發測試平台與 Testbench，執行模組與系統級驗證。 9.撰寫技術文件、模組規格書與驗證報告，確保設計品質與可追溯性。 您需要具備的條件： 1.電子、電機、資工等相關科系碩士以上學歷。 2.具備 5 年以上 ASIC 數位設計與驗證實務經驗。 3.熟悉 Verilog/SystemVerilog RTL 設計與模擬驗證流程。 4.熟悉 ASIC 設計流程，包括 Synthesis、STA、DFT、FPGA 驗證等。 5.熟悉 AMBA 介面協定（AXI、AHB、APB）與上層 IP 整合方法。 6.熟悉 UVM 驗證架構，具備自行開發 testbench、scoreboard、coverage model 經驗。 7.具備完整晶片設計與量產（含 Tape-out）經驗者佳。 8.熟悉低功耗設計方法（如 clock gating、UPF）者佳。 9.具備 ARM 或 RISC-V MCU 開發經驗者佳。 10.有密碼演算法或資安相關模組設計經驗者尤佳。 相關報導： 2025 國家科學及技術委員會舉辦「AI創新應用論壇暨IC Taiwan Grand Challenge頒獎典禮」 獲優秀團隊獎 https://ynews.page.link/xzLbF 2025 台灣最大AI競賽「智慧創新大賞」經濟部智慧創新大賞 IC新創及中小企業奪得「 金獎」 https://news.m.pchome.com.tw/living/twpowernews/20250503/index-17462668050674847009.html 量子電腦資安攻防戰！振生半導體首創PUF+PQC市場唯一最佳解方https://udn.com/news/story/7240/7917935 EE TIMES 報導：振生半導體引領IC安全創新 https://www.eettaiwan.com/videos/jmem-technology-leads-ic-security-innovation/ 2024 台灣新創世界杯「振生半導體奪冠」　10月赴美爭百萬美元投資款 https://finance.ettoday.net/news/2786606

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）開發相關的數位RD職缺。 【將負責的工作內容】 1. RTL design & verification 2. Customer support and debug 3. MIPI,USB, PCIE等高速介面IP開發。 4. 不同製程的IP Porting。 5. PHY Test Chip整合。 【條件與特質】 1. 具備數位設計流程經驗 (Synthesis/LEC/DFT/ATPG/STA) 2. 熟悉完整的Tape out flow 3. 熟悉MIPI,USB,DDR(LPDDR)相關高速混合信號介面(PHY)尤佳 4. 有數位IC設計工程師相關工作經歷3年以上 5. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

【產品線描述】 Smart TV Solutions：提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions：提供智能手機、智能電視、電競螢幕、AI Server等產品各種ASIC(包含CoWoS/ChipLet平台)解決方案 【工作說明】 1. 執行SoC IC 設計開發，整合驗證，量產規劃。 2. 高整合 SoC 架構設計與整合規劃 ( Smart TV、FRC)。 3. 應用COWOS、Chiplet 、ADAS的專業知識，解決設計挑戰，持續更新技術趨勢。 4. 先進製程 RTL to Netlist 設計流程規劃與實踐 ( low power、synthesis、STA、LINT、CDC)。 5. 與 APR 合作，確認 Implement (Placement、CTS、Route) & Sign-off (IR、STA、Thermal) 設計品質 。 【必要條件】 1. 電機/電子/通訊/電信工程相關科系 2. 需具備數位電路設計基礎

【產品線描述】 Evolution Video Display 新興顯示器開發： 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕，極致沉浸競界曲面螢幕，遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器，極窄邊框拼接電視牆，電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器)，車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 【工作說明】 電路硬體設計與開發 1. 顯示器或車用顯示系統架構開發 (System Architecture Development) (a) CPU/MCU架構整合 (b) SoC system bus 與 bridge架構規劃設計 Familiar with AXI/AHB/APB/Arbiter (c) DDR memory controller 2. 高速數位介面 High-Speed I/F (a) HDMI TX/RX link layer (HDMI1.4/2.0/2.1) (b) DP TX/RX link layer (DP1.4/2.0) (c) MIPI RX link layer (d) Vx1 link layer (e) USB Type-C controller 3. Picture Quality(PQ) (a) 視訊影像處理,色彩轉換演算法開發有興趣或具經驗 (b) HDR10+, Dobly Vision 4. FPGA 平台設計 5. APR flow (a) Synthesis/STA (b) DFT (c) Low-power flow (d) APR co-work 【必要條件】(熟悉或有相關經驗) 1. 顯示器或車用顯示 CPU/MCU/DDR controller/bus bridge相關經驗 2. 高速數位介面 High-Speed I/F HDMI TX/RX / DP TX/RX / Vx1 相關經驗 3. Picture Quality(PQ) 視訊影像處理經驗 車用相關IC 設計經驗 4. SOC 整合經驗

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking