「數位IC設計工程師IV-台北」的相似工作

1. 光通訊產品相關高速介面數位設計 (112G PAM4 SerDes) 2. 依據系統規格, 執行架構設計以及撰寫硬體描述語言 (RTL) 3. 具有高速介面, 低功耗, 以及D/A混合電路設計經驗者尤佳

1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA

1. Project integration support & implementation, to deliver qualified nestlist from RTL. 2. preSTA/SYN/LEC/postSTA/etc. EDA flow execution and enhancement 3. Timing & power closure 4. Schedule control, netlist optimization, flow coordinator

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之數位控制。 2. 熟悉Verilog與FPGA開發流程，了解High-Level Synthesis開發技術。 3. 具有實作數位訊號處理與數位架構設計於FPGA之經驗。

Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA

工作內容： 1. 數位IC電路設計，模擬驗證及下線 2. 數位IC設計流程，包括Linting、Synthesis、DFT、STA...等. 3. FPGA硬體設計 相關應用: 1. 電源管理IC數位電路設計 2. Interface protocol design - I2C、PMBus、SPMI、I3C...etc. 3. Power management state / sequence / fault / charger control...etc. NVM (eFuse/OTP/MTP) controller

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

請在您投遞履歷時同時回答您以下問題! 1: 你為什麼想加入一家早期AI邊緣運算公司？ 2: 假如這家公司未來三年內無法保證升遷與高薪，你仍願意投入嗎？為什麼？ 3: 你是否願意融資前薪資略低，但享有融資後股權參與機會？ 4: 我們這邊沒有華麗的資源，也沒有很多人手，甚至連教育訓練也不完備，你來這裡就是要跟我一起摸黑開路。你願意嗎？ AI 邊緣運算 IC / IP 設計 RTL Coding / Functional Verification FPGA 驗證與系統整合

- Experience with memory controllers (e.g. DDR DRAM, eMMC and other flash, etc.) - Experience in CPU or various buses (AXI, etc) - Good verilog writing skills - Willingness to work with a variety of tasks

1. 負責數位電路設計和RTL 和IP design, 模擬和驗證. 2. 與類比設計和系統設計, 佈局設計工程師溝通和協作. 3. 實現FPGA emulation和測試平台開發. 4. 協助量產測試程序的開發. 5. 規格書和Design Document的撰寫. 6. 工作地點在台北內湖

我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容： ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求： 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗 4. 對開發人工智慧((AI) 晶片與邊緣運算有興趣者

1.RTC Module/ IP design. 2.Design synthesis. 3.Design verification. 4.DFT/ siemens tools.

【成為円星人】 円星科技由一群專業與充滿熱情的夥伴創立於2011年，為積體電路矽智財設計服務業之新秀，秉持著『成為半導體業最值得信賴之IP公司』的願景，追求永續經營與成長。 誠摯歡迎您成為円星人，加入我們，站上國際舞台！ 一起共同打拚，以精品文化之精神，創造價值，追求卓越！ 【職務簡介】 M31主要業務為向 IC 設計業者和晶圓代工廠授權 IP，此職務為負責高速介面 IP（High Speed Interface IP）開發相關的數位RD職缺。 【將負責的工作內容】 1. RTL design & verification 2. Customer support and debug 3. MIPI,USB, PCIE等高速介面IP開發。 4. 不同製程的IP Porting。 5. PHY Test Chip整合。 【條件與特質】 1. 具備數位設計流程經驗 (Synthesis/LEC/DFT/ATPG/STA) 2. 熟悉完整的Tape out flow 3. 熟悉MIPI,USB,DDR(LPDDR)相關高速混合信號介面(PHY)尤佳 4. 有數位IC設計工程師相關工作經歷3年以上 5. 電機電子/資訊工程碩士畢業 如果您有以上相關經驗且對此職缺有興趣，歡迎投遞您的履歷！

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

驅動IC/觸控IC/指紋辨識IC晶片相關數位電路開發

1.負責CPU設計的功能驗證，包括建立和維護驗證環境。 2.制定和實施約束隨機驗證策略，以確保CPU和相關外圍設計的功能正確性和性能。 3.運用覆蓋率驅動的方法來進行低功耗驗證，確保設計在各種功耗模式下的穩定性和效率。 4.實施形式化驗證和斷言基礎驗證，以提高設計的可靠性和降低錯誤率。 5.分析和處理驗證過程中出現的問題，與設計團隊緊密合作以進行問題定位和修正。 6.撰寫和維護相關的技術文檔，包括驗證計劃、測試案例和驗證報告。 7.跟踪最新的驗證技術和工具，不斷優化驗證流程和方法。

a. Job Description: We are looking for a highly motivated RTL Designer to join our team in developing high-performance digital IPs. The ideal candidate will have experience in Register Transfer Level (RTL) design and verification, with a strong understanding of digital logic, microarchitecture, and ASIC/FPGA development processes. The role involves designing and verifying custom hardware IPs for cutting-edge applications. b. Verification: Develop and execute test plans to verify functionality, performance, and power requirements. Create testbenches using SystemVerilog/UVM for functional verification. Perform simulation, debugging, and root cause analysis for design issues. Conduct code coverage and functional coverage analysis to ensure comprehensive testing. Collaborate with verification and firmware teams to validate IP functionality. c. Qualifications: Bachelor’s/Master’s degree in Electrical Engineering, Computer Engineering, or a related field. 2+ years of experience in RTL design and verification. Proficiency in Verilog, SystemVerilog Strong understanding of digital design concepts, including pipelining, clock domains, and low-power design techniques. Experience with simulation tools (e.g., ModelSim, VCS, Questa) and formal verification techniques. Familiarity with UVM methodology and testbench development. Knowledge of scripting (Python, TCL, Perl, Shell) for automation. Experience with FPGA or ASIC development flows, including synthesis and timing analysis. Strong debugging and problem-solving skills. Excellent communication and teamwork abilities. - Non smoking

【About Us】 VICI Holdings' Hardware team is seeking a Senior Digital Design Engineer to join our dynamic group. In this role, you will be pivotal in advancing our trading systems, contributing to the development and enhancement of cutting-edge technologies. We boast the leading digital hardware development team in Taiwan and possess FPGA design technology in parallel with wall street trading firms. This expertise enables us to build ultra-low-latency, fully automated trading systems. Our trading strategies cover stocks, futures, and derivatives, achieving a daily global trading volume in the hundreds of millions dollars. 【Roles/ Responsibilities】 • Micro-architecture, design and implement high-performance digital circuits optimized for low-latency application • Develop high speed data paths, ensuring minimal logic depth and efficient pipeline • Optimize critical paths and combinational logic to reduce propagation delays and improve throughput • Work with Verilog/ SystemVerilog to implement RTL design • Apply parallelism and resource sharing techniques to enhance performance and throughput • Develop latency-aware micro-architectures for real-time processing and networking applications • Debug, optimize and iterate on designs using FPGA platform and cycle-accurate simulation • Work closely with digital/system verification engineers to ensure functional correctness and performance validation • Take ownership of FPGA verification tasks to ensure design correctness and performance. • Develop and execute verification plans for high-speed IPs such as PCIe, Ethernet, and Switches. • Support system validation engineer to debug FPGA issue Design Collaboration: • Collaborate closely with Algorithm, software, design validation and application team to define micro-architecture Performance Analysis: • Conduct performance testing and analysis, ensuring the low-latency goals are met across various use cases. • Capability to solve routing timing issue and analysis FPGA timing report result. 【Candidate Requirements】 • Master’s degree or above in EE, CE, or CS, plus 3–8 years of high-speed digital-design experience • Hands-on experience in IP-level digital-circuit design or IP integration (preferred) • Proficient in debugging and optimization with VCS and Verdi simulation tools • Comfortable working in Linux/Unix environments • Strong analytical and problem-solving skills with a performance-driven mindset 【Other Requirements】 • Proven ability to solve complex design challenges and deliver robust solutions • Experience designing ultra-low-latency data paths—arithmetic units, multiplexers, FIFOs, registers—for high-performance applications (preferred) • Familiarity with FPGA verification tools such as Quartus or Vivado (a plus) • Knowledge of high-bandwidth memory interfaces (DDR, HBM, etc.) • Understanding of networking protocols (Ethernet, PCIe, etc.) 【Interview Process】 • Resume Screening → HR Phone Screen → Face-to-Face Interview (with 30-60mins on-site coding test)