[Responsibilities]
★ Experienced in ISP (Image Signal Processing)
★ Plan design architecture.
★ Develop high quality digital design.
★ Be familiar with IC design flow.
[Minimum Qualifications]
★ Outstanding problem analysis and debugging skills.
★ Experienced in C language.
★ Experienced in Verilog RTL language
★ Experienced in digital IC design front-end flow
★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler
[Preferred Qualifications]
★ Nice to have experiences in scripting language.
★ Nice to have experiences in FPGA flow