1. Responsible of preparing, coordinating and technical supporting Marvell SoC/ASIC projects using IPs developed by Marvell Central Engineering.
2. Preparation includes kick-off with BU and customer (if needed) about IP usage, risk assessment and IP/package/test board/test plan review, etc in pre-silicon phase as well as providing regular interlock and training to Marvell internal BUs.
3. Coordination includes driving the best engineering resources for SoC bring-up and issue debug until stable production is achieved.
4. Technical support is essentially using the knowledge and experience about Marvell PHY and supporting analog IPs to resolve any system and IP level issues observed from SoC bring-up to production.
5. The IPs are mostly Marvell multi-data rate high-speed SerDes as well as supporting analog IPs like analog bias, clock buffer and generator, process monitor, temperature sensor, etc.
6. The high-speed interface applications of interest are Ethernet single channel 10G/25G/50G/100G/200G KR/CR/C2M/C2C, PCIe Gen1-Gen6, CPRI, JESD, CEI, etc.
## Job Description:
- Planning and establishing pass/fail criteria for LEO satellite product testing (e.g., OTA, Thermal Vacuum, Radiation, etc.).
- Execution and result analysis of LEO satellite product testing.
- Writing test reports and documenting anomalies
- Developing and maintaining automated testing programs to improve testing efficiency.
## Skill:
- Familiarity with RF or phased array testing is preferred.
- Familiarity with Python and basic instrument control is preferred.
- Familiarity with military and space testing standards is preferred.