「HW Applications Engineer, Digital/Baseband (Taipei)(3069097)」的相似工作

請務必投遞官網(13021): https://careers.synopsys.com/job/hsinchu/applications-engineering-staff-engineer/44408/87733350400 You Are: You are an innovative and resourceful engineer with a deep curiosity for solving complex technical challenges at the intersection of hardware and software. With a strong foundation in Electronic Engineering, Computer Science, or a related field, you are adept at leveraging your programming expertise—whether in Python, Tcl, Perl, or similar languages—to streamline and enhance engineering workflows. Your experience within UNIX/Linux environments equips you to navigate high-performance computing scenarios with ease. You thrive in collaborative, cross-functional teams and are energized by the opportunity to work closely with top-tier foundry partners and leading fabless companies. Your keen understanding of physical verification flows—such as DRC, LVS, PERC, FILL, and DFM—sets you apart, and you are eager to deepen your expertise in SoC physical design enablement, process effect analysis, and signoff. You are detail-oriented, capable of producing clear technical documentation, and communicate with clarity and empathy across diverse audiences. What You’ll Be Doing: 1.Delivering advanced physical verification solutions (DRC/LVS/PERC/Fill) for top-tier foundries and key fabless customers, ensuring high-quality silicon signoff. 2.Developing and validating process design kits (PDKs) and verification methodologies in collaboration with R&D and customer teams. 3.Partnering with R&D to innovate and improve Synopsys tools and flows, contributing to the evolution of physical verification technologies. 4.Providing hands-on customer support, troubleshooting issues, and delivering timely resolutions that enhance customer satisfaction and product adoption. 5.Coordinating with internal teams, including product managers and end-users, to align on best practices and ensure seamless integration of new technologies. 6.Documenting technical solutions, validation methods, and customer workflows for knowledge sharing and process improvement. 7.Staying up to date on industry trends and applying new insights to continuously optimize verification processes and tools. The Impact You Will Have: Accelerate the adoption and success of Synopsys physical verification products in leading-edge semiconductor manufacturing processes. Drive the development of robust PDKs and methodologies that enable customers to achieve first-time-right silicon. Enhance the quality and reliability of Synopsys verification tools through direct feedback and collaborative innovation with R&D teams. Strengthen Synopsys’ reputation as a trusted partner to top-tier foundries and fabless customers worldwide. Facilitate faster product cycles and reduced time-to-market for customers by delivering efficient and effective signoff solutions. What You’ll Need: BS or MS degree in Electronic Engineering, Computer Science, or a related field. Proficiency in at least one programming language, such as Python, Tcl, or Perl. Hands-on experience with UNIX/Linux environments and command-line tools. Familiarity with physical verification flows (DRC, LVS, PERC, FILL, DFM) and understanding of complex layout/electrical design rules. Strong investigative, analytical, and problem-solving abilities, with a passion for learning new technologies. Ability to produce clear, concise technical documentation and validation reports. Prior knowledge of tool/runset development/support and experience with SoC physical design is a plus.

We are seeking a highly experienced and detail-oriented Senior Hardware Board Development Engineer with 10–15 years of hands-on experience in hardware system design. This role focuses on the development of evaluation boards (EVBs) and customer reference boards (CRB) for advanced SoC/ASIC platforms, including board-level architecture, high-speed signal design, and system bring-up. You will work closely with SoC/ASIC design teams, firmware engineers, and validation teams to deliver robust reference platforms for internal and customer use. The ideal candidate has deep expertise in DDR4/DDR5, PCIe Gen4/5/6, high-speed SerDes, and power delivery networks, along with strong debugging and lab skills. Responsibilities * Lead the design and development of SoC/ASIC evaluation boards, including schematic capture, PCB layout review, and component selection. * Perform board bring-up, signal integrity validation, and system-level debugging. * Collaborate with cross-functional teams to support SoC/ASIC validation and customer reference designs. * Conduct SI/PI simulations and optimize high-speed interfaces (DDR, PCIe, Ethernet). * Generate technical documentation including schematics, BOMs, test procedures, and design guides. * Interface with vendors and manufacturing teams for prototype builds and production support.

【本職缺優先審核至高通官網投遞人選】 【Talents who apply job through Qualcomm Career Website will be reviewed and considered as top priority】 https://careers.qualcomm.com/careers/job/446700329587 【General Summary】 As a CPU Verification Engineer, you will be responsible for verifying design features across all aspects of CPU. 【Roles and Responsibilities】 • Develop deep understanding of CPU micro-architecture. • Work closely with design/verification teams within CPU to develop comprehensive test plan. • Use simulation and formal verification methodologies to execute test plans. • • Write checkers, assertions and develop stimulus. • Verify power intent through use of methodologies like UPF. • Work closely with system architects, software teams and Soc team to validate system use cases. • Work closely with emulation team to enable verification on emulators and FPGA platforms. • Debug and triage failures in simulation, emulation and/or Silicon. 【Minimum Qualifications】 • BS degree in CS/EE – with course work in computer architecture. • Experience with programming languages – C/C++ and scripting languages – Perl/Python. • Experience with hardware description languages – System Verilog/VHDL. • Implementation of assembly and C language embedded firmware • Experience with software tool chain including assemblers, C compilers, Makefiles, and source code control tools 【Preferred Qualifications】 • Strong understanding of micro-processor architecture. • Strong understanding of power management, physical design concepts. • Experience in Silicon bring up and validation of CPU features. • Experience in debug of functional, power, performance and/or physical design issues in silicon. • Experience in CPU design and verification. • Experience in Test development for validation of CPU features on Silicon. • Experience in development of test vectors for tester bring up.

• Design high speed PCBs for Ethernet applications including performing pre and post layout signal and power integrity simulations. • Perform PCB layout and signal/power integrity design reviews. • Effectively plan and organize board build process, component procurement, board bring-up, debug, and testing to ensure technical objectives and schedules are met. • Interact with cross-functional teams like design, marketing, software and validation on their board requirements and update status on the board builds.

1. Define GPU compiler software architecture and interfaces. 2. Development/implement GPU compiler pipeline, linking and various optimizations/transformations. 3. Collaborate with Driver team, HW team to implement new API & HW features. 4. Collaborate with Driver team, HW team to improve/tune performance & power consumption. 5. Execute & deliver to meet milestones/schedules. 6. Analyze and debug code generation issues. 7. Analyze and influence future GPU architectures. 8. Construct reliable & trustable relationships across teams internally & externally. 9. The position can be located at Hsinchu or Taipei

1. 主動式電子掃描陣列 (相控陣列) 射頻元件及電路板佈局設計。 2. 評估與天線、熱控、電源、及機構之整合相容性，並進一步除錯和優化。

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: - Verification of the ASIC design, architecture, and micro-architecture of PCIE controllers for multiple product generations for GPUs, SOCs & DPUsat IP/sub-system levels using standard verification methodologies such as UVM and Specman/e. - Develop UVM or Specman/e based testbench components reusable across verification methodologies and integrate those across verification environments. - Build or improve reusable testbench components including constraints, stimulus, monitors, checkers and scoreboards following coverage based verification methodology. - Understand complex testbench and its verification scope with respect to the design specification and implementation, define new verification scope as per design or verification methodology requirements, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. - Collaborate with multiple verification teams, architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see:  - B.Tech./ M.Tech. with 2+ years of relevant experience - Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog - Background with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) - Experience in developing and working in functional coverage based constrained random verification environments - Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd:  - Knowledge of PCIE protocol - Gen3 and above - Proficiency in Testbench development using SystemVerilog - Perl, Python or similar scripting and SW programming language experience - Good debugging and analytical skills - Good interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

1.Support Design Engineer on Signal Integrity testing and Debugging on Chip and Demo Board 2.Support Customer projects design-in stage to mass-production. 3.Support Customer projects design review (Schematics, layout, CTS report) 4.Team work with RD, AE and QA on debugging and problems solve.

1. 無線通訊系統設計與驗證 (WiFi, BT, GNSS, NFC, …etc.) 2. 無線通訊系統相關的認證、Debug 與對策 (FCC, CE, SAR …etc.) 3. RF de-sense. 4. 無線通訊模組的技術審查.

Purpose of this Position 深入研究高速訊號，在高速硬體電路Signal Integrity上提供最佳設計且確保生產品質 Major Areas of Responsibility 專案研發 - Perform high speed signal integrity simulation including 10G/40G、25G/100G、PCIE、SATA、DP、USB、DDR3/DDR4/DDR5. - Perform pre-layout, layout constraint, and post-layout simulation processes. - PCB stackup design and layout review for high speed signal and PDN. - Build component models to ensure the correlation between SI/PI simulation and measurement. - Solid SI experience in resolving technical issues and performing detailed analysis. 團隊合作 - Collaborating with EE teams to refine high-speed signal performance. - Collaborate with the layout engineer to provide clear layout guidelines and enhance footprint optimization.

1. 主動式電子掃描陣列 (相控陣列) 雷達系統之硬體電路設計。 2. 熟悉RF PCB Layout Guideline與PCBA廠商管理。 3. 理解SI/PI的觀念。

【Who We Are?】 Hytech是一個年輕、充滿活力的團隊，專注於推動金融科技行業的企業技術轉型，是全球領先的管理技術諮詢公司。創新思維和扁平化的管理，讓團隊成員以公開、透明的方式自在工作，也為全球客戶提供卓越的商業價值服務。 【Why Join The Team?】 Hytech 團隊在共事的過程中核心技術會與時俱進，即時討論，並且有良好的溝通管道，扁平化管理，任何問題或意見都可以討論及合作解決。密切的與跨國同事團隊交流。 【About The Role】 隨著 Hytech 的全球規模與業務持續擴大，我們誠摯邀請Software QA Engineer軟體測試工程師加入團隊，以產品品質為導向，不斷提升服務品質。共同邁向成功。 【身為團隊的一份子您將負責】 1. Actively participate in the Scrum incremental software development process, collaborating with the development team in daily stand-up meetings, retrospectives, and reviews to ensure smooth progress in development and testing. (積極參與 Scrum 漸進式軟體開發流程，與開發團隊進行每日站會、回顧與檢視，確保開發與測試進度順利推進) 2. Break down testing tasks based on project requirements, estimate timelines and resource planning, and coordinate manual testing, automated testing, smoke testing, stress testing, UAT testing, and production validation. (依據專案需求拆解測試任務，進行時程評估與人力規劃，安排手動測試、自動化測試、冒煙測試、壓力測試、UAT 測試及上線驗證) 3. Responsible for designing, reviewing, and managing test cases to ensure test coverage and effectiveness. (負責測試案例的設計、評審與統一管理，確保測試覆蓋率與有效性) 4. Lead and manage a team of 30+ QA Engineers, overseeing task allocation, performance, and development. Collaborate closely with cross-functional teams, including R&D, Product Management, Operations, and the PMO, to ensure seamless quality assurance across the development lifecycle. (管理並領導一支超過 30 人的 QA 工程師團隊，負責工作分配、績效監督與團隊發展。與跨部門團隊密切合作，包括研發、產品管理、營運與專案管理，以確保產品開發全流程中的品質保證無縫接軌) 5. Utilize Jira for project management, tracking bug statuses, analyzing test data, identifying issues, and providing timely solutions. (運用 Jira 進行專案管理，追蹤 Bug 狀態、數據統計，並即時發現與解決問題) 6. Maintain a strong commitment to product quality, paying attention to detail while managing multiple concurrent projects. (對產品品質高度負責，注重細節，能同時處理多個並行專案) 7. Analyze and summarize online issues, optimizing testing processes to reduce future occurrences. (分析與歸納線上問題，並優化測試流程以降低未來發生率) 8. Actively communicate and coordinate to drive cross-functional collaboration and ensure product quality standards are met. (積極溝通與協調，推動跨部門合作，確保產品品質達標)

1、主要負責藍芽通訊系統的硬體設計以及RF性能驗證 2、有無線射頻電路設計基礎，熟悉微波通訊或天線設計為佳 3、熟悉BQB&FCC驗證為佳

1. 無線通訊RF電路的設計、優化、驗證(LTE, WiFi, BT, NFC, GPS等) 2. 設計規格評估、線路圖與電路佈局設計 3. 射頻系統共存Co-existence分析、De-sense對策、EMC射頻法規問題改善 4. 協助產品導入生產線量產

請提供[英文履歷] 職缺說明 本職缺為硬體測試工程師，主要負責自駕車相關電子模組與硬體的測試開發工作。需具備硬體測試設備設計與自動化能力，並與設計工程師、製造商及跨部門團隊合作，推動產品開發及測試流程優化。 工作內容 - 功能測試規範與要求：制定自駕車電子模組與硬體的功能測試規範與需求。 - 測試設備設計與建置：設計並建置生產自動化測試設備及製具，包括高階方塊圖、線路圖、測試儀器電路圖及使用者操作手冊(SOP)。 - 故障模式分析與測試優化：與設計工程師及代工廠合作，識別故障模式並制定故障排除測試計劃，推動產品開發及測試流程改進。 - 製造測試整合與訓練：協助代工廠將測試設備整合至生產線，並負責測試團隊的訓練。 - 測試軟體開發與優化：開發與修改現有測試軟體，並撰寫測試序列以提升測試效率。 - 跨部門合作：與電子工程師、軟體工程師、生產測試工程師及專案經理緊密合作。 所需專業與技術 - 學經歷：電子, 電機或相關技術領域學士學位，3 年以上相關測試開發經驗。 - 產線測試站開發能力：熟悉測試站的硬體與軟體相關開發。 - 測試與除錯經驗：熟悉實驗室設備操作、硬體系統除錯及製造測試流程。 - 專案經驗：曾參與專案，從prototype 階段推進至量產階段(MP)。 - 溝通能力：具備優秀的書面與口頭英文溝通能力，能有效與內部及外部合作夥伴互動。 - 代工廠進度追蹤與問題討論：每週需前往代工廠（新北/新竹），進行進度追蹤與問題討論。 優先考慮 - 軟體技能：熟 Linux 環境，並能使用 Python 或 NI LabView 開發軟體。 - 具備雷達毫米波技術(mmwave) 相關經驗。 - 數位通信匯流排：熟悉至少一種數位通信匯流排技術，如 CAN、I2C、SPI、MIPI、DDR 或 PCIe。

Role Summary/Purpose: Hardware design engineer will closely work with worldwide engineers to perform engineering works for hardware testing solution of next generation semiconductor devices. The work includes requirement analysis, feasibility study, solution evaluation, task planning, project management, design execution, quality control and verification. We are working on cutting edge requirement and future technology. Responsibilities: • Provide global semiconductor interface test hardware solutions of next generation semiconductor devices for world-wide customers • Provide chip test interface HW solution engineering to compare pros and cons of different approaches and recommend best option to customers considering both performance, lead time, cost • Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc. • Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up) • Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage • Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges. • Responsible for global end to end hardware project management to ensure best quality and on time delivery -Device testing requirement assessment and Feasibility study -Risk analysis and mitigation planning -Schedule planning and project management -Design execution -Regular review with global internal and external customers -Quality Control and Verification • Work closely with Global supply chain, provide solution to solve manufacture (DFM), assembly (DFA) challenges, ensure hardware products on time delivery and very high first pass rate • New technology research, new products, new materials evaluation for next generation device testing • Deliver hardware design training and seminars to customers

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU & SOC acts as the brains of computers, robots, and self-driving cars that can understand the world. We are looking for System Power Validation Engineer in Taipei for board/system power qualification and function test, responsible for NVIDIA Data Center platform, Graphics board, ARM Based platform and Autonomous Driving Platform. If you're creative and autonomous, we want to hear from you! What you'll be doing: • DC-DC Power measurement. • DC-DC Power solution testing and debugging. • Co-work with hardware design engineers on debug and FA. • Co-work with mechanical/thermal engineers for cooler/heatsink design. What we need to see: • Bachelor/Master in EE, computer science, or relative majors. • Familiar with Linux OS. • Good English communication skills. • Good PC system/platform knowledge. Ways to stand out from the crowd: • Proactive personality. • Good team player. • Strong desire on creativity. • Quick thinking.

* Complete responsibility of PHY Validation in post-silicon environment * Defining, documenting, executing, and reporting the overall PHY validation/test plan for Marvell storage devices * Lab-based silicon bring-up and unit test execution focused on Physical and PCS layer hardware and firmware functionality * Perform high speed signal validation and analysis using various test equipment to measure Eye diagram/Jitter/BER * Analyze and debug issues on Phy protocol of storage interface (SATA, SAS, PCIe, Ethernet) * Troubleshoot failing tests with diagnostics, software tools, hardware analyzers, oscilloscopes, meters, logic/protocol analyzers * Lead collaborative technical discussions to drive resolution on technical issues * Work with cross-functional teams and external vendors to debug any post-silicon and/or customer issues related to Ethernet/PCIe PHY * Work closely with customers to address design issue and debug failure cases

##職務說明 - 相控陣列系統(通訊/雷達)射頻電路(PA/LNA/Mixer/Filter/PLL)架構規劃、模擬及電路設計。 - 根據系統規格進行電子元件評估與選用。 - 與Layout工程師、結構工程師溝通、協調並完成電路、佈局設計及確認 - 電路板及系統層級效能測試、驗證、除錯並將產品導入量產。 - 執行產品研發流程及技術文件產出 ##技能需求 - 具電路 RF / Analog / Digital 電路三年以上設計經驗 - 熟悉量測儀器使用 - 具備基礎焊接能力

• Develop production and characterization ATE test programs and hardware. Understand test requirements, test methodologies and test strategies. • Collaborate with Design teams on new products from debug, characterization to full production. • Manage production test programs at various manufacturing sites. Support new product qualification and transfer. • Identify & drive test cost reduction and yield improvement projects. • Align test engineering systems/processes for various manufacturing sites