「M000-資深產品工程師」的相似工作

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

1. Foundry Tapeout Account 申請。 2. Foundry 製程能力評估和Tapeout 與良率提升。 負責評估Foundry製程能力，Tapeout 作業，持續推動製程優化，進而提升產品良率。 3. 跨單位工程問題協調 代表公司與客戶、Foundry、封裝廠及光罩公司協同解決各項工程相關問題。 4. 產品流程管理與分析 負責從Tape Out、Mask Job Review到產品量產的全流程管理，並進行與協力商處理ESD與Latch Up分析。 5. 封裝評估與導入,與測試數據分析. 6. HTOL QUAL 和 Package QUAL可靠度測試,與RMA分析. 7. 異常問題查證與製程改善 當產品異常發生時，運用EFA/PFA找出低良率原因，並與RD、Fab及Assembly部門協作解決，持續推動製程改善。 8. 熟悉Packaging(WLCSP、wire bond、Molding...)與Testing(CP、FT...)各階段等，知道如何與Test Engineer/外包討論ATE平台、測試coverage、bin split 等議題 9. PDK及相關文件管控 主導PDK及相關文件的申請作業，並與PM/RD團隊密切合作，嚴格控管文件版本，確保資料一致性與最新狀態。 10. 主管交辦事項.

1. Foundry co-work and contact window. 2. Handle co-development of power, MCU related applications , mass production & yield ramp up . 3. It's better with Foundry process integration or product experience.

1. 產品電性量測分析與測試報告產出 (MOSFET、DC-DC IC、AC-DC IC) 2. 產品規格書製作 3. 新產品單體與系統驗證 4. 協助客戶問題回覆(需跨部門合作以及客戶溝通)

● 光學模組機構設計 ● 光學系統架設與檢測分析 ● 光學系統相關技術專利佈局 ● RF射頻電路設計與分析 ●矽光子產品DC/RF量測與分析

1. Device characterization and test key design. 2. 元件量測並提供desinger相關規格數據 3. 記憶體陣列設計

一、工作內容： 1.產品技術導入規劃 2.彙整報告提交 3.電子料件承認審核 4.BOM確認 5.ECN會議招開 6.不良品分析 7.品質系統相關產品資料作業 8.主管交辦事項 具EMS廠相關經驗尤佳

1. 熟悉FAB 8”wafer Driver、Power Driver IC (DC-DC)/CSP Module等產品製程相關經驗 2. 具備量產WAT/CP/FT driver產品良率分析與異常處置 3. 熟悉電性分析、FA失效分析工具、Yield Hub 等良率分析軟體操作經驗 4. 良率改進、供應商管理 5. 協助QA客訴異常分析/驗證與root cause問題查找分析處置經驗 6. 其他主管交辦事項 辦公地點分為 1.新北汐止辦公室(台灣科學園區T3館) 2.新竹竹北辦公室(富翼大樓) 【工作待遇依工作經歷敘薪】

1. MP Management (50%) 1-1. Yield improvement and cost reduction activities. 1-2. Abnormal Lot disposition, diagnose problems and offering a solution with the balance of efficiency and quality control. 1-3. Foundries/OSATs capacity expansion planning and executing. 2. NPI(New product introduction) Management (35%) 2-1. Coordinate new Tape-out schedule and release to MP activities. 2-2. Perform and consolidate product reliability qualification. 3. Cross-department support, consolidate specific activities. (10%) 4. Advanced foundry process technology survey and implementation. (5%)

Reporting to MOSFET Development Manager, you will work as Sr. MOS Development Engineer to be responsible for process integration, development and optimization. About the job: Work with product designer to create new device structure ideas and develop the necessary Mosfet/ IGBT /Diode technologies Closely work with internal process experts and external foundry partners to set up the required technologies and processes to produce the prototypes and with test labs to assess results vs. simulations / expected behavior. Responsible for experimental matrix design to evaluate and optimize design vs. specification. Co-work with fab engineering teams to generate the final design rule menu and electrical parametric specifications. Participation in fab selection and evaluation for future foundry locations. Participate and help the Design Engineers and Product Engineers on reverse engineering analysis when necessary. Act as the internal expert of semiconductor devices and processes to provide the necessary information and advices to designers on new technologies. Short term travels for business trips and trainings. About you: Knowledge of semiconductor device physics, such as Diode, BJT, MOSFET, and IGBT…etc and understanding of complex interactions between different fabrication processes. Experiences in semiconductor process development, and basic knowledge in semiconductor device characterization. Ability of arranging tests with 3rd party labs and comfortable with working in Lab for device characterization. Good writing/reading/communication in English is a MUST. The ability to operate independently in a cross-cultural working environment. Experiences in both conventional Bipolar, CMOS, DMOS processe Understanding or experiences in power semiconductor devices assembly and applications would be preferred. Knowledge and experiences of material analysis or Failure analysis tools, such as SRP, SIMS, SEM…etc. Familiar with mask generation, wafer fab process flow and in-line/PCM specifications. Knowledge and experience in one or more of the following areas would be a plus, but not must: o Test pattern generation o Semiconductor process/device modeling o Basic assembly & test processes.

1.Conduct feasibility studies before product kick-off. 2.Coordinate with the R&D team and other related teams. 3.Check new technology/design rules. 4.Manage new product development. 5.Prepare product samples for testing. 6.Perform competition analysis.

1.新評估項目導入，稽核及品質相關會議安排與執行，有品質管理經驗佳。 2.具有客戶服務意識和了解客戶需求能力，能夠主動回應客戶並提供有效的解決方案。 3.廠商客戶品質問題的處理與回覆、後續的分析追蹤與執行。 4.撰寫與審核8D Report，具備英文撰寫能力及良好跨部門溝通能力，針對品質問題進行追蹤處理。 5.協同維護氣體鋼瓶及化學品更換，氣體及化學產品出貨與倉儲管理。 6.異常排除，緊急應變處理，需多元性發展以協助其他專案報告及設備相關維護活動。 7.主管交辦事務執行。

1. 測試良率分析改善 2. SOP 撰寫 3. 異常分析與改善 4. 流程改善與生產效率提升 5. 新客戶/新產品導入

【職務內容】 1. 新產品設計功能驗證/測試程式開發/量產導入 2. 電性分析EFA/產品參數規格特性分析 3. Dram test coverage enhancement 【其他條件】 1 Memory Product engineer/Testing engineer. 2 Good ability in using Advantest(T5503,T5593, T5583) to test.

1.產品生產測試流程規劃及導入。 2.分析測試資料、釐清問題、提出改善建議，並撰寫測試報告。 3.與供應商合作開發新封裝及量產導入。 4.跨部門合作與溝通(開發、製造及品保…等)，確保產品品質。 5.完成交付任務。

1.五年以上,能獨立完成無塵室規畫/監造經驗者。 2.案件會勘/設計/標單填寫整理。 3.業主溝通協調,請款處理。 4.工程分包安排及延續性工程業務處理。 5,工程部人員管理,溝通協調,調派,文件審核。

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

1.提供客戶技術服務，必要時須至現場協助客戶 2.產品技術資料準備 3.協助業務推廣產品與技術支援 4.具備專案管理能力 5.熟悉電力單線圖 6.主管交辦任務執行

1. 產品範疇為車床、銑床、木工產業及其產業應用 2. 新產品新市場需求瞭解及規格訂定 3. 同業產品資料收集與研究分析 4. 公司內外連結橋樑，評估及反應客戶需求 5. 新產品開發計劃、推展計劃擬定與進度追蹤 6. 控制器功能開發、人機介面設計、工具軟體開發 7. 機電整合與馬達伺服系統應用 8. CAM軟體開發設計及應用

UltraSense Systems, headquartered in Silicon Valley, is revolutionizing human-machine interfaces (HMI) through its cutting-edge SmartSurface technology. Our InPlane Sensing platform seamlessly integrates touch, lighting, and haptic feedback into everyday surfaces, delivering intuitive, responsive, and premium user experiences across automotive, consumer electronics, and other industries. Join our mission to create the next generation of smart, touch-sensitive surfaces that are both functional and aesthetically superior. Summary UltraSense Systems is seeking a creative Senior Engineer, Ultrasound Algorithm Development to help develop the prototype of a groundbreaking new product. In this role, you'll collaborate with a high-caliber team to design and build devices that break new ground in the industry. This role involves hands-on algorithm development, acoustic signal processing, and system development. Key Responsibilities ．Lead design, development, and prototyping of ultrasound sensor systems—from concept through testing and iteration (inspired by Xwave Innovations roles) ．Develop, implement, and optimize acoustic signal processing algorithms, including beamforming (phased array/delayandsum), synthetic aperture techniques, and advanced array processing ．Write clean, efficient, well-documented Python code for simulation, modeling, and real-time signal acquisition/processing ．Build and integrate prototype hardware and firmware components (e.g., piezoelectric transducer interfacing, digitizers, array electronics) ．Conduct simulations, modeling (e.g., FEA or acoustic propagation), and validation testing; iterate to improve system performance ．Analyze sensor data, benchmark performance metrics, debug acoustics chain (from raw signals to processed outputs), and refine algorithms and hardware　accordingly ．Collaborate with cross-functional teams—mechanical, electrical, software—to define system requirements and drive integrative design (common across R&D roles) Minimum Requirements ．Degree: M.S. or Ph.D. in Electrical Engineering, Acoustics, Computer Science, Applied Physics, or a related field ．Hands-on experience (3–5+ years) in acoustic/ultrasound signal processing or sensor systems, including beamforming and array processing (phased arrays, delay-and-sum, synthetic aperture, etc.) ．Strong proficiency in Python for algorithm development, data analysis, and simulation (e.g., with NumPy, SciPy, MATLAB not essential but a plus) ．Practical experience with prototyping hardware—working with transducers, pulser/receiver logic, data acquisition systems, or similar instrument interfacing ．Solid understanding of acoustic wave propagation, ultrasound physics, signal-to-noise enhancement techniques, and array signal processing principles ．Excellent communication, writing, and documentation skills; ability to draft technical reports, collaborate with teams, and present findings clearly (noted across industry postings) Desired Requirements ．Ph.D. in relevant field, with a proven R&D track record, including publications, patents, or conference papers ．Experience with FEA modeling or acoustic simulation tools, especially for transducer design or wave propagation analysis ．Background in device fabrication, CAD design, or microelectronic processing (e.g., GDS patterning) is a plus ．Familiarity with synthetic aperture ultrasound techniques or advanced imaging methods ．Experience developing adaptive or data-driven beamforming (e.g., deep learningenabled approaches for ultrasound) ．Proficiency in embedded platforms or real-time firmware, including porting signal processing algorithms into C/C++ or FPGA/ASIC environments ．Proven ability in small R&D environments—self-motivated, resourceful, and highly collaborative ．Comfortable working in a fast-paced, cross-functional environment ．Creative thinker with a passion for tackling unfamiliar challenges ．Eagerness to contribute to early-stage product innovation and development