1. Main responsibility is to design analog IPs in MCU such as adc/dac, pll, osc, por, ldo
2. 具備DC-DC Converter, Buck相關電路設計
2. Responsible for analog IP design, verification plan, test plan, document
3. Communicate with system, layout and digital engineer to ensure high quality
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雅特力科技創立於2016年,為智原科技子公司。
【Artery雅特力】即將在台上市的IC設計公司,主要產品為32bit ARM core base MCU
公司網址:https://www.arterychip.com
關於雅特力:https://www.104.com.tw/company/1a2x6blojm
We are seeking a skilled Analog IC Design Engineer with expertise in MIPI TX/ PLL design and sensor readout circuits. The ideal candidate will possess a strong foundation in analog design and a passion for developing cutting-edge solutions in a collaborative environment.
1.Design and implement MIPI TX and PLL circuits for high-speed data transmission.
2.Develop charge pump and LDO (Low Dropout Regulator) circuits to ensure efficient power management.
3.Design and optimize oscillator (OSC) circuits for precise timing applications.
4.Create sensor readout circuits, including CDS (Correlated Double Sampling), TDC (Time-to-Digital Converter), ramp circuits, DAC (Digital-to-Analog Converter), and comparators.
5.Collaborate with system engineers to define specifications and ensure alignment with overall project requirements.
6.Perform circuit simulations and analyses using tools such as Cadence, Spectre, or HSPICE.
7.Conduct design verification and validation through prototyping and testing.
8.Optimize designs for performance, power efficiency, and reliability.
9.Participate in design reviews and contribute to project documentation.
10.Provide support during the layout and fabrication process.
Preferred Qualifications:
1.Familiarity with IP design principles.
2.Experience with mixed-signal circuits.
3.Knowledge of low-noise and high-speed design techniques.
Digital IC design engineer
- Familiar with Verilog RTL coding
- Familiar with digital design flow (pre-layout simulation, timing constraint, synthesis, post-layout simulation)
- Will be working on high speed Serdes IPs
- Experience or interest in all-digital PLLs or clock-data recovery circuits is a big plus
【產品範疇】
1.Touch panel controller
2.TDDI
【工作內容】
1.Analog front-end design
2.ADC design
3.Switched-capacitor circuit design
4.負責layout floorplan規劃,與layout工程師合作完成相關驗證
【需求條件】
1.Device physics knowledge applied to analog IC design
2.Familiar with analog IC design flow
3.Familiar with Hspice or Spectre
1.Design and maintain analog circuits
2.Survey and maintain design processes
3.Survey and maintain design tools and flow
4.Help training junior engineers
5.Debugging and measuring chip