新竹市3年以上碩士以上
[General Summary]
As a forward-thinking technology company, Augentix advances the limits of innovation in "Industrial and Embedded IoT" to deliver next-generation experiences and accelerate digital transformation toward a smarter, more seamlessly connected world.
As a DRAM System Engineer at Augentix, you will be responsible for bringing up and validating DRAM subsystems across our embedded platforms. You will work at the intersection of hardware and low-level software to ensure memory stability, performance, and power efficiency under demanding workloads. This role offers the opportunity to lead system-level debugging, performance tuning, and test automation for DDR3/LPDDR3/DDR4/LPDDR4 memory interfaces, while collaborating closely with hardware, SoC, and kernel teams across the product development lifecycle.
[Responsibilities]
★ Lead DRAM bring-up and validation for DDR3/LPDDR3/DDR4/LPDDR4 on new hardware platforms.
★ Configure memory controller and PHY registers to meet JEDEC specs and system performance requirements.
★ Perform signal integrity validation and work with hardware team on layout constraints and SI/PI tuning.
★ Conduct stress tests and margin sweeps (e.g., memory hammer test, data retention, read/write window tuning).
★ Analyze system-level memory stability and performance under boot-up, suspend/resume, and runtime workloads.
★ Collaborate with SoC, PCB, firmware, and kernel teams to debug memory-related issues.
★ Develop and maintain automated test flows and diagnostics for DRAM reliability and performance.
★ Occasional business travel across APAC and other regions may be required.
[Minimum Qualifications]
★ Master's degree in Electrical Engineering or a related field with 3+ years of relevant experience, or a PhD in a related field.
★ Strong understanding of DDR3/LPDDR3/DDR4/LPDDR4 specifications, timing parameters, and calibration schemes.
★ Experience in configuring DRAM registers and bring-up on embedded platforms.
★ Familiar with memory controller architecture and PHY interface tuning.
★ Skilled in using logic analyzers, oscilloscopes, and memory test equipment.
★ Comfortable with Linux-based embedded systems and debugging low-level software interactions with DRAM.
[Preferred Qualifications]
★ Experience debugging kernel panics or stability issues caused by DRAM misconfiguration.
★ Familiarity with memory low-power states, self-refresh, and power-saving strategies.
★ Knowledge of post-silicon validation, including test pattern development and validation coverage planning.
★ Worked with DRAM vendors to understand datasheets, tuning recommendations, and errata.
Comfortable working in a globally distributed, cross-disciplinary engineering team.