「數位IC設計副理/經理(Power IC)」的相似工作

1. 具有數位電路設計以及RTL coding基礎者 2. 熟悉EDA tool 3. 驅動IC相關經驗者優先

(a) 負責Tcon IC開發 (b) 負責數位影像處理IP開發 (C) 1.整合使用 FPGA IP，具模擬驗證以達功能的需求 2.系統驗證項目的規劃及系統整合與測試 3.開發、撰寫及驗證 Verilog code (D) 1.使用System Verilog、UVM驗證數位IP 2.依據規格擬定測試計畫並建立隨機測試向量 3.與Design Team密切合作，提高function/code test coverage

This vacancy is open for talent pool collection. We will contact you if we have proper vacancies that fit with your profile. Job Mission Represent manufacturing and act as gatekeeper from manufacturing to D&E function Add value in overall manufacturing processes such as forming, machining, joining, and assembling Job Description Contribute to the solution of faults and takes the necessary initiatives and practical decisions to ensure zero repeat Identify gaps and drive assigned process improvement projects and successful delivery Initiate and drive new procedure changes and projects Develop and maintain networks across several functional stakeholders Prioritize works and projects based on business situation Transfer knowledge and train colleagues on existing and newly introduced products Education Master degree in technical domain (e.g. electrical engineering, mechanical engineering, mechatronics) Experience 3-5 years working experience in design engineering Personal skills Show responsibility for the result of work Show proactive attitude and willing to take initiative Drive for continuous improvement Able to think outside of standard processes Able to work independently Able to co-work with different functional stakeholders Able to demonstrate leadership skills Able to work in a multi-disciplinary team within a high tech(proto) environment Able to think and act within general policies across department levels Diversity and inclusion ASML is an Equal Opportunity Employer that values and respects the importance of a diverse and inclusive workforce. It is the policy of the company to recruit, hire, train and promote persons in all job titles without regard to race, color, religion, sex, age, national origin, veteran status, disability, sexual orientation, or gender identity. We recognize that diversity and inclusion is a driving force in the success of our company. Need to know more about applying for a job at ASML? Read our frequently asked questions.

數位IC設計

1. Integrate and modify USB2.0 controller IP 2. Solve issues and plan CP/FT of USB projects 3. Design and verify digital circuits.

1. IC產品之研發與應用設計 2. 建立IC產品基礎規格並設計IC電路 3. 降低產品成本，提高IC品質，支援軟/硬體開發 4. 熟數位IC設計及相關工具 Verilog HDL、Cadence IES simulator 、FPGA tools、Synopsys DC

1. Speech/LCD 相關 ASIC 設計開發 2. IC spec訂定討論 (含 analog IP spec) 3. 數位電路設計、整合及 Back-end flow 4. 跨部門 IC 驗證 5. 協助處理良率及客訴問題

【產品範疇】 LCD – Mobile TDDI/車載/平板/工控 【工作內容】 1.Verilog RTL電路的設計與驗證 2.Chip及 IP 整合, DFT 及 Cad Tools 設計流程及驗證 3.CP/FT測試規劃及產出test pattern 【需求條件】 1. MS or PhD degree in EE, or relevant fields 2. 熟悉Verilog HDL, IC Design CAD Tools（simulation, synthesis, LEC, STA, etc.） 3. Whole-chip整合、邏輯電路設計及相關IC設計流程

## 職務說明 - 應用於無人機雷達系統 - 數位IP架構設計與實作。 - 透過MATLAB/C++協助數位IP驗證 - 透過FPGA整合與驗證。 ## 技能要求 - 具備數位訊號處理經驗 - 具備數位電路設計經驗 - 程式語言必要：Verilog/VHDL, TCL, ##加分條件： - 具備雷達/通訊訊號處理、數位設計架構 - 具備RF/Analog 知識與RF/Analog校準設計 - 程式語言: MATLAB, python, c, c++, Chisel3

1. 專案整合服務之諮詢、接案討論及分析執行 2. 相關工程問題回覆與專案報告撰寫 3. 案件排程與實驗資料判讀 4. 交期回報/實驗資料傳送 5. 回報案件daily status與主管交辦事項 6. 與國外客戶討論相關分析案件 7. 小夜班津貼優於業界 8. 年薪依個人表現而異，表現優異之資深工程師年薪可達100萬，表現優異之工程師年薪可達85萬

1. Foundry co-work and contact window. 2. Handle co-development of power, MCU related applications , mass production & yield ramp up . 3. It's better with Foundry process integration or product experience.

We are seeking a highly skilled DFT/DFM Engineer to join our automotive ADAS SoC chip design team. The successful candidate will be responsible for DFT and DFM methodologies, design, and implementation for our advanced automotive system-on-chip (SoC) designs. The candidate will also collaborate with the design and layout teams to integrate DFT/DFM requirements. • SoC testing architecture design • Support project NPI(new product introduction) to MP(mass production) (test program development, coverage enhancement, yield improvement, cost reduction) • Cowork w/ IP, test engineer, process team, board design to fulfill CP/FT/SLT test requirement.

1. 負責數位IC設計整合: a. 依客戶需求設計整合IC功能、工作頻率、介面規格、消耗功率等基本規格 b. 完成SoC系統架構設計，並依功能單元運作屬性區分區塊規格 c. 使用Verilog/VHDL編程內部功能並撰寫RTL code 2. 負責功能驗證與除錯 a. 制定功能驗證計畫 b. 審核驗證計畫的完整性和正確性 c. 進行基本模擬，確認RTL code的功能 d. RTL code寫入FPGA晶片連接系統測試，驗證RTL code 3. 負責時序分析與功耗管理 a. 產出邏輯閘級電路連線網表(netlist) b. 進行SoC系統的時序分析 c. 進行SoC系統的功耗分析 4. 其它主管交辦事項 【必要條件】 1. 電機、電子、資訊工程或相關科系，碩士以上學歷 2. 三年以上 SoC 設計或整合經驗 3. 熟悉CPU子系統設計整合 a. 熟悉 ARM 架構， b. 對 RISC-V 架構有基本認識 4. 熟悉數位IC前端設計流程，如RTL design、Lint/CDC、Synthesis、STA、LEC、ECO等 5. 具類比IP整合相關經驗，例如PHY、Serdes、PLL等 6. 熟悉IC後段設計流程，如DFT、MBIST、P&R、post-cilicon system level debugging等

【在華邦，學習不設限，讓AI技術力與你的未來力同步成長!】 我們深信「人才永續」是企業創新的核心動能。華邦持續投資於數據素養與AI應用的培育，支持每一位人才掌握AI與數據應用的核心能力。 ．內部學習平台提供超過4,000堂線上課程，其中包含近850堂資料科學、人工智慧、數據思維與程式技術等多元主題，支援彈性自主學習 ．建立跨部門的 AI實作班與技術社群，定期舉辦研習與交流活動，讓知識轉化為實戰力 ．完善數據應用學習資源，結合資料呈現(Power BI、Tableau)、資料處理(Python、JMP)、流程自動化(Power Automate、UiPath)、AI助手(Copilot)，協助同仁有效以數據驅動決策與創新。 ．搭配專業語言學習平台，提供學習補助與資源，鼓勵同仁持續進修，拓展國際視野 無論你是技術新秀還是資深專才，華邦鼓勵所有領域都能與AI結合，與國際接軌。持續精進、突破自我！ 【邀請您將104履歷同步上傳至華邦官方網站，將使您的履歷優先被主管看見】此職缺履歷登錄網址:https://bit.ly/4lHkbzD [工作內容] 1. Responsible for design and development of digital ICs, including Verilog RTL coding, functional verification, and optimization. 2. Participate in the complete ASIC design flow: specification, RTL design, synthesis, static timing analysis, and physical design handoff. 3. Perform Design-for-Test (DFT) implementation, including scan insertion and MBIST, to support manufacturability and testability. 4. Support SoC integration, including bus protocols (AMBA) and high-speed interfaces (PCIe, SerDes).

⚠️特別說明：此職位需on-site在新竹清大創新育成中心辦公室，無提供遠端工作條件。 ✅主要職責： 1. 高效能記憶體子系統（DDR/LPDDR Subsystem）之整合、開發與驗證。 2. 參與GenAI SoC設計，包括架構規劃、RTL設計、模擬與驗證。 3. 配合後端設計團隊，進行時序分析與設計優化。 5. 進行設計文件撰寫與維護，確保設計過程符合公司開發流程。 6. 針對客戶需求，進行系統分析與客製化設計開發。 ✅基本要求： 1. 電機、電子、資訊工程相關科系畢業，學士以上學歷。 2. 具備5年以上數位IC設計經驗。 3. 熟悉 DDR PHY 架構、控制器、timing calibration與 training 流程 4. 熟悉SoC Bus Fabric設計，具備AXI、AHB等匯流排介面經驗。 5. 熟悉RTL設計 (Verilog / System Verilog)。 6. 了解前端設計流程，包括模擬、合成、時序分析等。 7. 良好的問題分析能力，具備團隊合作精神。 ✅加分條件： 1. 有參與過 LPDDR Subsystem Integration與Silicon Tape-out 並成功量產 2. 熟悉 Synopsys LPDDR、Cadence GDDR IP/Subsystem 3. 熟悉 UPF、低功耗設計流程 4. 熟悉 DFT 、Scan、BIST ✅ Why Join Us 1. 與頂尖技術團隊共事，參與高效能 AI/高速記憶體解決方案開發 2. 自主創新文化，提供技術發揮與產品影響力兼具的工作環境

[job description] Wolley is seeking candidates for a digital design engineer position. You will join an experienced team designing next-generation memory, storage controllers, and high-speed interface standard. You will also contribute to design concept discussion, architecture definition, as well as design implementation. ‧ Architecture design and RTL implementation ‧ System bus and related peripheral designs ‧ SoC and emulation platform design ‧ SoC system performance analysis [Requirement] 1. Bachelor's or Master's degree in Electrical Engineering or related fields 2. Familiar with RTL design, SystemVerilog, front-end design flow 3. The following working knowledge is desired: * Python programming * TCL scripting * Universal Verification Methodology (UVM) * Low power design and analysis

1. Architecture design and RTL implementation of Automotive/Smartphone chipset 2. SoC system power and performance analysis 3. SoC system bus and memory subsystem design, integration, and modeling 4. SoC low power design, integration, and modeling 5. SoC functional safety analysis, design, integration, and modeling 6. SoC cyber security analysis, design, integration, and modeling

1. 相關面板系統驅動應用 2. TV/MNT/NB TCON IC 相關驗證 3. 驗證平台設計與驗證 熟悉eDP PSR I/II ,DSC and other special feature verification & trouble-shooting尤佳

【工作內容】 • Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market • Provide the technical leadership to the DV team for the project • Work independently on various DV tasks and provide technical guidance to the DV team. • Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup 【職務條件】 • Master’s degree in Electrical Engineering, Computer Science, or related. • Good understanding of ASIC design verification flow. • RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences. • Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc. 【其他條件】 • MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification • MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.

Job Description: Are you ready to push the boundaries of what's possible in technology? Join the trailblazers at Sandisk. As a Principal Engineer you will be at the forefront of designing high-performance SoCs for storage solutions. By leveraging your expertise in RTL design and modern tools like GitHub Copilot, you will enhance the design process and productivity. You will collaborate with cross-functional teams to deliver groundbreaking solutions that meet our high standards of quality and performance. Key Responsibilities: • Innovate, implement, and verify RTL code for complex ASICs. • Performed design tasks across various design stages. • Utilize advanced AI-driven tools, including GitHub Copilot, to streamline the design process. • Collaborate with hardware and software teams for seamless integration. • Provide mentorship to junior engineers. • Stay abreast of the latest industry trends and emerging technologies in AI and ASIC design. Qualifications: • Bachelor’s or master’s degree in electrical engineering, Computer Engineering, or a related field. • Hands-on experience in digital IP/SoC design: minimum 7 years with a Bachelor's degree, or 6 years with a Master’s degree. • Proven experience in ASIC RTL design, with a strong grasp of Verilog/System Verilog. • Familiarity with the whole digital design flow. • Proficiency in leveraging AI tools, including GitHub Copilot, for design and development. • Strong problem-solving skills and the ability to thrive in a dynamic environment. • Excellent communication and teamwork abilities. Preferred Qualifications: • Experience in low-power design techniques and methodologies. • Familiarity with high-speed interfaces (e.g., SD Express, Compact Flash, PCIe, DDR). • Proficiency in scripting languages (e.g., Python, TCL) for automation. About Sandisk: Sandisk, a leader in data storage solutions, is seeking talented and experienced ASIC RTL Design Engineers to join our cutting-edge team. Our mission is to revolutionize the data storage industry through relentless innovation and technology breakthroughs.