「功率模組封裝設計主管」的相似工作

1. 產品簡報與資料彙整，與業務至客戶端拜訪並針對產品其技術性內容進行簡報。 2. 蒐集業界電源與工業馬達產業的技術資料，分析市場需求及同業狀況，並提供研發策略建議。 3. 提供經銷商/客戶產品的教育訓練。 4. 協助客戶選型，解釋datasheet規格。 5. 解決並追蹤客戶產品應用/技術問題。 6. 歸納整理技術文檔。 7. 現場支援(on-site support)，針對客戶遇到的異常協助排查。 8. 可配合國內外的出差。

•Design reliability test plan process for device life time evaluation •Coordinate with third party suppliers on device WAT/CP •Coordinate with third party suppliers on reliability test and failure analysis of power devices

1、產品設計審查及測試驗證、RD會議參與 2、APQP , PPAP , CP , MSA , SPC , FMEA六大核心工具應用 3、測試規範解析與導入 4、稽核應對

1. 封裝固晶(Die-Bond)製程作業。 2. 固晶(Die-Bond)相關設備保養維護、異常排除、效能改善、改機調機。 3. 封裝固晶(Die-Bond)製程改善與開發。 【本職缺可透過104應徵，也歡迎直接至穩懋官方網站投遞，增加履歷曝光度】請至穩懋官方網站投遞個人履歷表，此職缺履歷登錄網址：https://www.winfoundry.com/WinTalentPool/JobRequirement/Edit/1047

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1.Communicate with customer/partner and subcontractor to define the package design requirements, or specifications. 2.Propose the package size, structure according to requirements and specifications from customer. 3.Design the package and optimize to meet product specifications, coworking with related layout, electrical and thermal engineering teams. 4.Prototyping document preparation 5.Link with suppliers and follow up the development trend.

Overview: MOSFET Design Team offers the innovative environment for talents to dive deep into the world of device design, platform development, and research. We offer working locations in both Xindian and Tainan. Come and join us to focus on the most cutting-edge semiconductor materials and applications! Key Responsibilities: • Develop and execute innovative device layouts in line with customer requirements, ensuring optimal functionality and efficiency. • Partner with PE and Quality teams to enhance device reliability and address any arising issues in time. • Establish and continuously optimize SPICE models to reflect the characteristics of both new and existing devices. • Work alongside the PIE team and collaborate with external foundries, paving the way for the next generation of advanced devices. • Drive the research and patenting efforts centered around novel designs, applications, and advanced materials, such as GaN and SiC. • Accomplish additional tasks delegated by the supervisor. Qualifications: • A Master’s degree in EE, Physics, or a related field. • Expertise in power devices, with a spotlight on UMOS, SGT, LDMOS, MLSJ, GaN and SiC. • Comprehensive understanding of device physics and semiconductor manufacturing processes. • Proficiency in semiconductor simulation tools. • Strong English communication skills, catering to both technical and non-technical stakeholders.

1.生產計劃和生產執行、例行長假及突發事件的生產因應計畫執行； 2.各班生產人力制定與人員出缺勤管理及管控； 3.每月、每季、每年生產人員的績效評核與年度晉升評核； 4.操作人員的訓練計劃及實施執行； 5.間接原物料及雜項物品領用及使用管理、治工具使用耗損及生產設備之配置或淘汰換新管理； 6.生產環境管理及維護、設備資產與物料盤點； 7.品質及生產力改善、異常品、不合格品的處置執行及廢料管理。

(1) VB6 / C# / Java 程式開發 (2) 熟悉 SECS/GEM, EAP及相關自動化系統之開發與維護 (3) 機台測試資料處理, 有 Tango 系統維護經驗尤佳 (4) TCP/IP 協定程式開發經驗, 熟悉 Windows / Linux / Unix 作業系統 (5) 有封測半導體自動化經驗尤佳

1. Ensure PKG design is optimized with SI/PI/Thermal requirements. 2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model. 3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools. 4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design. 5. Provide the Substrate manufacturing process and material property. 6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise. 7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis. 8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB. 9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain. 10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations. 11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements. 12. Familiar with assembly and substrate manufacturing process is a plus. 13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent. 14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus. 15. Working with ASIC/HW/Production team.

製程整合/元件開發

We are seeking great talent to help us build The DNA of tech.® Vishay manufactures one of the world's largest portfolios of discrete semiconductors and passive electronic components that are essential to innovative designs in the automotive, industrial, computing, consumer, telecommunications, military, aerospace, and medical markets. We help the world's most in-demand technologies come to life. Every day our products touch your life and the lives of people across the world, though you likely do not know it. Come join us and help us build The DNA of tech.™ Vishay Intertechnology, Inc. is a Fortune 1,000 Company listed on the NYSE (VSH). Learn more at www.Vishay.com. Do you want to help us build the DNA of tech.? Vishay is currently seeking applicants for a Senior Product Engineer AUTO. You will be responsible for overseeing all phases of product engineering, new product development and production support for our Automotive Mosfet product line. Job Location: The ideal candidate will be working remote near one of our Vishay offices in Taipei, Taiwan Newport, UK. What you will be doing: • Hands-on technical ownership of new and established products within the Automotive MOSFET Division • Leads and manages new product introduction of leading-edge products from product definition and development through to characterization, qualification, and release phases, liaising with Market development, R&D, Package, Device design and other manufacturing organizations • Supports product problem solving with manufacturing, CQM, Product marketing and Application organizations within a fast-paced Automotive customer environment • Defines technical management presentations related to technical problems and project status • Liaise with Europe and Asia Pacific wafer fabrication and package assembly operations and engineering teams in yield enhancement and quality improvement programs • Defines and reviews Automotive product datasheets and technical specifications • Define statistical test methods to optimize yield and drive quality defect reduction programs • Organizes and reviews electrical and thermal characterization data and formulates device datasheets for new product releases • Supports cost reduction programs through engineering lot evaluations What you will bring along: • BS Degree in electrical engineering, Physics or Microelectronics or similar (Masters preferred) • 7 + years Product engineering experience or similar field with good knowledge of Discrete Power MOS semiconductor devices and Trench MOS Technologies Strong multi-tasking project and technical skills are required to drive new product introduction from product definition through to device characterization, qualification and final datasheet release to sales • Strong experience in product / process problem solving using statistical data analytics leading-edge yield management software Experience in the support of offshore facility to facility product transfers (package and wafer) • Familiarity with Automotive AEC Q101 testing and qualification requirements/ methods is a plus • Familiarity with MOSFET semiconductor ATE (automatic test equipment) Wafer and Package test methods are an advantage • Must have experience in interfacing with offshore Product Engineers - Europe - Asia- USA and drive international teams in a collaborative and time conscious fashion • Familiar with 8D and FMEA processes and concepts • Must be willing to travel to offshore sites in USA, Asia and Europe **Please make sure to attach your most updated English resume along with your 104 application.

1. Develop power device. 2. Design new device architectures and layout to meet customer's request. 3. Work closely with foundry team to reach mass production of the new process. 4. Device reliability judgment and analysis.

1. MOSFET device research and development, especially Trench MOSFET/ SGT/ SJ. a). Define device layout design and product design rule b). TCAD simulations to build device structure c). Device measurement d). DOE plan for MOSFET new product 2. Interface with Product engineer and Marketing. 3. EFA/ PFA for trouble shooting 4. Build related patent for new design

1、主要負責工程部門團隊組織運作、人員日常督導。 2、負責設定部門目標和組織架構。 3、計畫和執行新生產技術導入、產品移轉、規劃及進度追蹤。 4、計畫和執行生產設備維護導入。 5、評估和計畫新產品製程、測試計畫。 6、監督製程計畫、測試計畫。 7、促進提升設備改善、人力精簡、和自動化作業。 8、帶領各種專案的計畫和執行。 9、產品試產或量產階段產線工程問題改善、良率提升。 10、產線異常分析及改善對策擬定。 11、協調相關單位解決製程異常。 12、負責部屬培育、績效評估、回饋與改善。

1. 產品電性量測分析與測試報告產出 (MOSFET、DC-DC IC、AC-DC IC) 2. 產品規格書製作 3. 新產品單體與系統驗證 4. 協助客戶問題回覆(需跨部門合作以及客戶溝通)

1. 負責高分子材料均溫板(VC)等創新散熱模組的設計、開發與驗證。 2. 使用3D繪圖軟體 (ProE/Creo, SolidWorks) 進行機構設計、繪製與尺寸定義。 3. 運用熱流分析軟體 (Flotherm, FloEFD, 6SigmaET等) 進行散熱效能模擬、分析與方案優化。 4. 建立產品測試計畫，主導樣品的功能與信賴性驗證，並進行數據分析與報告撰寫。 5. 研究新型散熱材料特性，並評估其導入新產品的可行性。 6. 與材料、製程及業務團隊緊密協作，解決專案開發過程中遇到的技術問題，推動專案順利量產。 7. 提供客戶專業的散熱技術諮詢與解決方案。

1. (功率)保護元件開發 (如：齊納二極體 (Zener)、靜電保護 (ESD)、瞬態電壓抑制二極體 (TVS)…等) 2.對外：與客戶討論產品應用設計、電性、客訴…等議題；對內：產品電性、良率提升之改善。

【職務概述】 您是否熱衷於將創意轉化為現實？在前電，我們正在尋找一位充滿熱情與洞察力的「NPI 新產品導入專案管理師」，加入我們的前沿技術團隊！您將成為新產品從概念到市場的推動者，負責帶領跨功能團隊克服挑戰、實現突破，並創造改變世界的產品。這不僅是一份工作，更是一個讓您挑戰極限、靈活應變並快速成長的舞台！ 【主要職責】 掌控全局：制定並執行新產品導入的專案計劃，確保每個階段都精準到位，從設計驗證到量產啟動。 橋接未來：與研發、製造、供應鏈及客戶團隊緊密合作，打破部門壁壘，讓創意順利落地。 迎接挑戰：快速診斷並解決專案中的技術與流程難題，提出創新方案，讓不可能成為可能。 靈活應變：根據市場需求與客戶反饋，動態調整專案策略，展現您的決策力與適應力。 驅動成長：監控進度、優化資源，並向高層展示您的成果，成為團隊中的關鍵影響者。 產品相關事務：功能、規格、認證、包裝、品質管理、進度及風險控管 跨單位溝通&資訊統整 配合市場需求開發新產品 【職務要求】 學士學位以上且電機電子相關, 材料化學學系相關尤佳 至少3-5年專案管理經驗，具NPI或產品開發背景者優先。 熟悉MS365各軟體工具, 流程優化方法。 出色的溝通能力，能在多元團隊中游刃有餘。 熱愛挑戰，具備解決問題的創意思維與抗壓能力。 英文流利（TOEIC 600分以上）。

【產品線描述】 Smart TV Solutions：提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions：提供智能手機、智能電視、電競螢幕、AI Server等產品各種ASIC(包含CoWoS/ChipLet平台)解決方案 【工作說明】 先進封裝 Package/substrate 設計工程師，主要規畫 SoC IC 封裝，整合開發驗証的 EVB 設計。 1. 負責IC floor plan, IO pin mux 及 PAD location規劃。 2. 負責 ball map 規畫, Substrate基板設計佈局。 3. 電路板開發 (EVB) 設計與除錯 【必要條件】 1. 須熟悉OrCAD, PADS and Cadence Allegro 等應用軟體。 2. 具備PCB/Substrate design及傳輸線理論等相關知識。 3. 具備電子電路，Power 架構設計， SI/PI概念。 4. 具一年以上BGA封裝設計, 熟悉各種類型之封裝及基板設計, 有 CoWoS 封裝設計經驗尤佳。 5 積極、跨部門溝通協調能力、有責任感 。