Role Summary/Purpose:
Hardware design engineer will closely work with worldwide engineers to perform engineering works for hardware testing solution of next generation semiconductor devices. The work includes requirement analysis, feasibility study, solution evaluation, task planning, project management, design execution, quality control and verification. We are working on cutting edge requirement and future technology.
Responsibilities:
• Provide global semiconductor interface test hardware solutions of next generation semiconductor devices for world-wide customers
• Provide chip test interface HW solution engineering to compare pros and cons of different approaches and recommend best option to customers considering both performance, lead time, cost
• Responsible for Testing circuits Design and super high layers PCB design for high complexity ATE device interface board correspond to various device testing, eg. Mobile application processor, High performance computer, AI, RF etc.
• Responsible for scheme selection of a SUBSTRATE/MLO design in wafer testing, research for low Cost of Test scheme (considering TDE, Skip DIE, substrate stack-up)
• Responsible for power integrity (PI) and signal integrity (SI) simulation at board level or system level, frequency domain or time domain to ensure HW product performance at design stage
• Implement complex mechanical design/simulation, cable design, thermal evaluation by collaborating with PCB design to achieve premium quality in hardware solution according to customer device testing ultimate challenges.
• Responsible for global end to end hardware project management to ensure best quality and on time delivery
-Device testing requirement assessment and Feasibility study
-Risk analysis and mitigation planning
-Schedule planning and project management
-Design execution
-Regular review with global internal and external customers
-Quality Control and Verification
• Work closely with Global supply chain, provide solution to solve manufacture (DFM), assembly (DFA) challenges, ensure hardware products on time delivery and very high first pass rate
• New technology research, new products, new materials evaluation for next generation device testing
• Deliver hardware design training and seminars to customers
We are seeking a highly experienced and detail-oriented Senior Hardware Board Development Engineer with 10–15 years of hands-on experience in hardware system design. This role focuses on the development of evaluation boards (EVBs) and customer reference boards (CRB) for advanced SoC/ASIC platforms, including board-level architecture, high-speed signal design, and system bring-up.
You will work closely with SoC/ASIC design teams, firmware engineers, and validation teams to deliver robust reference platforms for internal and customer use. The ideal candidate has deep expertise in DDR4/DDR5, PCIe Gen4/5/6, high-speed SerDes, and power delivery networks, along with strong debugging and lab skills.
Responsibilities
* Lead the design and development of SoC/ASIC evaluation boards, including schematic capture, PCB layout review, and component selection.
* Perform board bring-up, signal integrity validation, and system-level debugging.
* Collaborate with cross-functional teams to support SoC/ASIC validation and customer reference designs.
* Conduct SI/PI simulations and optimize high-speed interfaces (DDR, PCIe, Ethernet).
* Generate technical documentation including schematics, BOMs, test procedures, and design guides.
* Interface with vendors and manufacturing teams for prototype builds and production support.
【產品範疇】
1.DDI / TP / TDDI/ TCON/ Power等顯示相關產品
【工作內容】
1. SI/PI/EM issue solving, performance optimization, and design rule development
2. Chip/PKG/Board simulation and measurement for SI/PI/EM issue.
3. Co-work with system engineers, IC designers, and customers on product design-in tasks.
【工作內容】
• Work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market
• Provide the technical leadership to the DV team for the project
• Work independently on various DV tasks and provide technical guidance to the DV team.
• Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
【職務條件】
• Master’s degree in Electrical Engineering, Computer Science, or related.
• Good understanding of ASIC design verification flow.
• RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences.
• Knowledge of Perl, OVL, SVA, SV, UVM, OVM, script programming, etc.
【其他條件】
• MSEE with a minimum of 5 years, or BSEE with a minimum of 8 years of experience in digital ASIC/SOC design verification
• MS/BS degree in EE or CS with expertise in digital IP/SOC design verification.
1. Architecture design and RTL implementation of Automotive/Smartphone chipset
2. SoC system power and performance analysis
3. SoC system bus and memory subsystem design, integration, and modeling
4. SoC low power design, integration, and modeling
5. SoC functional safety analysis, design, integration, and modeling
6. SoC cyber security analysis, design, integration, and modeling