1.Improve process condition and upgrade process capability.
2.Working with a team of QA, other process and equipment engineers responsible for starting up, developing and optimizing processes to improve product quality and reliability, productivity improvement and risk management as well as resolving manufacturing line problems.
3.Identify, diagnose and resolve process related problems by applying failure analysis, FMEA, 8D or SPC methodology.
4.Handling process baseline qualifications and managing(Cpk, control limit review), auditing and risk management objectives.
1. Ensure PKG design is optimized with SI/PI/Thermal requirements.
2. Create the PKG/RDL/Subtract SI 3D modeling and perform extraction of S-Parameters and RLGC model.
3. Full-wave modeling of VIAs, Connectors, Package and PCB channels, components using 3D full-wave EM tools.
4. Provide the CM(Construction rules) and Design Rules(guidelines) for the PKG/RDL/Subtract design.
5. Provide the Substrate manufacturing process and material property.
6. SI(Signal integrity) simulation and optimization on package stack-up, power/ ground plane assignment and optimization, decoupling cap locations to minimize power ground noise.
7. PI(Power integrity) analysis for state of art package/system designs, which include but not limited to package layout model extraction, transient noise analysis to meet the silicon noise spec, decoupling strategy and analysis.
8. CTK(Crosstalk) analysis and reduction on-package considering mutual-effect by on-die, on-silicon interposer and on-PCB.
9. SSN(Simultaneous Switching Noise)/SSO analysis for I/O (DDR5/4/3, LPDDR5/4/3, etc.) power domain.
10. Eye diagram(ZRZ/PAM4) and jitter analysis for CPS(Die Chip-PKG-System PCB) co-simulations.
11. Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements.
12. Familiar with assembly and substrate manufacturing process is a plus.
13. Familiar with programming/scripting in Java, VBScript, PERL, TCL, MatLab and/or equivalent.
14. Experienced in SI PI automation tool development with Python or PyAEDT is a plus.
15. Working with ASIC/HW/Production team.