4/26 光電事業部-晶片技術研發主管
- 光寶科技股份有限公司
- 消費性電子產品製造業
- 新北市新莊區
- 5年以上
- 碩士
1. 負責光電半導體晶片開發藍圖規劃及管理 2. 負責新晶片的開發和進度管理 3. 建立晶片技術平台和管理 4. 協同客戶開發晶片需求技術 5. 提供晶片技術解決方案
1. 負責光電半導體晶片開發藍圖規劃及管理 2. 負責新晶片的開發和進度管理 3. 建立晶片技術平台和管理 4. 協同客戶開發晶片需求技術 5. 提供晶片技術解決方案
1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. Digital front-end design flow
1.1KW 以上Buck Boost DC/DC PWM 功率級與電感設計,系統測試除錯,線路圖繪製。 2.MCE節能系統Buck Boost PWM功率級研發,系統測試。 3. ESS/AFC儲能控制系統研發及測試。
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.
1 prefer the experience of running SI/PI simulation tools such as ADS,Ansys, Hspice, etc. 2.with knowledge of transmission line, microwave and electric circuit theory BA degree in Engineering, Computer Sciences or equivalent.
【工作職責 (Responsibilities)】: ★ ARM series CPU integration ★ System bus architecture design and implementation 【Professional Experience】: ★ Experienced in ARM series CPU integration flow (ARM9, CA7, etc.) ★ Experienced in ARM cache, MMU, TCM design ★ Experienced in system bus architecture (AMBA AHB/AXI) design ★ Experienced in SoC chip integration 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ Outstanding problem analysis and debugging skills. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler 優秀條件 (Preferred Qualifications): ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow ★ Nice to have experiences in C language.
【工作職責 (Responsibilities)】: Work with a team to: ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ MS degree in Electrical Engineering, Computer Science or related field. ★ Proficient in Verilog coding and verification. ★ Experienced in front-end IC design flow. 優秀條件 (Preferred Qualifications): ★ Experienced in C language. ★ Experienced in scripting language. ★ Distinguished organizing abilities. ★ Outstanding problem analysis and debugging skills. ★ Optimistic and self-driven personality.
Summary: Super Micro Computer, Inc. is seeking a talented Firmware Engineer who will be responsible for developing world-class firmware to fully maximize the strong hardware architecture of in-house servers. We are looking for talented individuals who enjoy creating firmware for computer server products, prototyping concepts, and investigating new technologies. In this position, the candidate will collaborate with cross-functional teams to design robust server products. Essential Duties and Responsibilities: Includes the following essential duties and responsibilities (other duties may also be assigned): • Responsible for porting, developing, testing documenting, and maintaining firmware for Server System. • Develop AOC/BPN/MB server products including FPGA/CPLD and MCU base designs. • Develop System Level Architectures for sub-system designs. • Build, test and troubleshoot hardware. • Dive into and take ownership for critical design issues, work with cross-functional teams for debugging and troubleshooting issues. • Participate in safety training and actively comply with safety policies and practices; maintain a clean and safe workstation.
1. 解決客戶應用技術問題,並回饋給相關單位。 2. 撰寫客戶端的技術文件與規格說明。 3. 提供客戶正確的產品規格與應用相關資訊,以作為客戶設計產品時的參考依據。 4. 提供客戶偵錯服務與技術支援,以協助發現並解決產品試產時所發生的問題。 5. 提供客戶量產測試工具,分析並解決量產時發生的問題。
負責先進製程實體設計(APR in 5nm/7nm), 包含physical synthesis(DCG), floorplan, powerplan, placement, CTS, routing, timing fixing and DRC/LVS, . . ., etc. 1. APR hierarchical design flow. 2. Physical design project execution. 3. Responsible for physical verification including DRC, LVS and ESD checking. 4. Static timing analysis by using Synopsys PrimeTime. 5. Work Assignments. 6. Interdepartmental communication and collaboration.
1.從事FPGA RTL撰寫/設計 2.自有IP(Intellectual Property)設計/研發 3.特殊高端產品FPGA應用
1. 研究V2X與人機介面可能面臨之安全攻擊 2. 研究底層實體網路可能面臨之安全攻擊 3. 研究重要資料與軟體/韌體之可能安全漏洞 4. 針對車用所需網路安全提出防護機制 5. 實作關鍵防護機制之軟硬體
1.開發multi-mode GSM/WCDMA/LTE L1 software 2.開發OFDM信號處理嵌入式系統 3.開發ASIP/DSP架構數位通訊系統
【工作職責 (Responsibilities)】: ★ Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing ★ STA timing analysis and fixing ★ Physical verification, including DRC, LVS, IR drop and DFM analysis. ★ Physical design flow development and automation 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ 電機、資訊相關科系,學士或碩士畢業 ★ 具有獨立思考的能力,並習慣與團隊合作解決問題 ★ 高度的學習動機、願意投入精力分析和解決問題 優秀條件 (Preferred Qualifications): ★ 具有IC相關 tape out經驗 ★ 熟悉Tcl, Python語言
【工作職責 (Responsibilities)】: ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. ★ Professional Experience ★ Experienced in image/video module design ★ Experienced in SoC front-end integration flow ★ In-house core algorithms' module design 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool ★ Familiar with video codec algorithm (H.264, H.265, H.266, AV1)
1.USB3.0 host/device開發驗證相關工作 2.RTL coding/synthesis/simulation/verification
Digital design verification using UVM and System Verilog.
1.Deep algorithm knowhow in the field of camera/display/CV/AIAR. 2.Strong algorithm IP architecture design capability including early-stage cost analysis, data flow define, memory access scheme optimization. 3.Team work with algorithm team for fixed-point algorithm and cost reduction algorithm developing. 4.Familiar with SystemC to RTL flow is plus.
1. 負責系統晶片RTL整合,協助晶片bring-up,除錯與特性分析 2. 協助建立FPGA 3. 與Power團隊合作power分析與收斂 4. 與Physical design團隊合作Timing收斂與達成晶片面積目標 5. 與驗證團隊合作驗證,並建議測試計畫與驗證的方法 6. 根據規格,整合公司內部與外部IP 7. 與系統部門合作,了解系統與電路結構與系統需求 職務需求 1. 有工作經驗,並且與驗證團隊與Physical design團隊合作過尤佳 2. 了解有低功耗設計方法 3. 對RTL與產生的電路認識 4. 了解 bus結構,具備各種嵌入式記憶體知識,與晶片通訊界面規格 5. 了解reset與clock結構,具備Power domain設計知識 6. 了解專案資料庫版本管理系統 7. 了解Lint,DFT,UPF, 合成 8. 有Chip top的整合者經驗者尤佳
1.UVM verification environment build-up 2.Expert in SystemVerilog and constraint random. 3.Behavior model design from spec and verification proposal define. 4.Experience in formal verification is plus.