5/03 IC Layout工程師
- 鯨鏈科技股份有限公司
- IC設計相關業
- 台北市信義區
- 3年以上
- 碩士
1. High-Speed Circuit (TX/RX, PLL, CDR),Mixed-signal Circuit Layout 2. IP layout 及chip 整合
1. High-Speed Circuit (TX/RX, PLL, CDR),Mixed-signal Circuit Layout 2. IP layout 及chip 整合
Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual will perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Signal matching / sensitive nets shielding technique • Pad / ESD rule and routing / connection • Database DRC & LVS verifications • Chip Tapeout in accordance with company's Tapeout Procedure • Positive Attitude Qualifications: • Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable
Job Summary: As an IC CAD engineer, you will collaborate closely with the design team to develop & maintain software/script solutions that enhance their workflow. This role involves operating within a multinational setting and participating in collaborative projects that demand cross-team coordination. Your responsibilities will encompass gathering requirements from these teams, devising a comprehensive plan, prototyping in a variety of programming languages, implementing an agile approach for ongoing project enhancements, and ultimately delivering a product aimed at enhancing overall team productivity. If you have a solid software background and decent knowledge on IC design, this is the job for you. Essential Functions: • Development of scripts for IC design automation. • Development of a continuous integration plus continuous delivery environment applied to IC design. • Data collection & visualization for design activities. • Document processes and flows. Qualifications: • Bachelor's degree in Electrical Engineering or Computer Science (MSEE or dual degree is preferable). • Fundamental grasp of Integrated Circuit design, encompassing Analog, Digital, or both. • Proficiency in Linux and basic Shell commands. • Proficiency in Python with main-stream packages / frameworks, such as Flask, Pandas, etc. • Elementary familiarity with web technologies, including JavaScript, Node, HTML, and CSS. • Capable of creating database schemas that accurately represent and facilitate business processes • Skillful in unit testing and debugging. • Experience with QT or PyQT • Competence in both SQL and NoSQL databases. • Proficiency with version control tools like SVN and Git. • Exposure to continuous integration, build tools (e.g., Jenkins, Ansible), and scripting.
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.
1. 研究V2X與人機介面可能面臨之安全攻擊 2. 研究底層實體網路可能面臨之安全攻擊 3. 研究重要資料與軟體/韌體之可能安全漏洞 4. 針對車用所需網路安全提出防護機制 5. 實作關鍵防護機制之軟硬體
• A Mixed-Signal Digital Design Engineer assists on the Analog Design and Analog-Digital interface definition, design, validation, verification and integration of mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions. • MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.
Working experience in PC industry or IC industry Language: TOEIC scores at least 800, or TOEFL iBT compatible Strong excel skill: Macro Work carefully on details Good team player and strong on coordination
1. MOSFET device research and development, especially Trench MOSFET/ SGT/ SJ. a). Define device layout design and product design rule b). TCAD simulations to build device structure c). Device measurement d). DOE plan for MOSFET new product 2. Interface with Product engineer and Marketing. 3. EFA/ PFA for trouble shooting 4. Build related patent for new design
1. New device/platform research and development, especially Transient Voltage Suppressor(TVS), ESD/Surge protection a). TCAD simulations to build process condition and device structure b). Define device layout design and product design rule c). EFA/ PFA for trouble shooting 2. Interface with Product engineer and Marketing 3. Build related patent for new design
1. 類比IC佈局(Layout)經驗,做過BCD Prcoess尤佳 2. 需要負責全晶片整合佈局和DRC/LVS之驗證
1. IC package substrate design and layout 1.1. Package type includes flip-chip and wirebond. Single die design and multi-die design 1.2. Substrate layer count from 2 layers to 20+ layers. Preferred experience is at least 4 layers (1-2-1) 1.3. High-speed (DDR, SerDes, PCIe...) signal routing optimization 1.4. Good knowledge in substrate layout design rules and package assembly design rules 2. Chip-Package-PCB co-design 2.1. Review die bump assignment and BGA ball assignment to provide suggestions to optimize the design
1. Design RF IC in WiFi and IOT applications including SW/LNA/SAW/MEMS filter/Filter...etc. 2. Design of circuit link budget, topology and novel scheme development. 3. Optimization with process, device and system. 4. Measurement and optimization, bring to product launch
●工作內容 1.具備電子電路相關概念,進行PCB Layout工作 2.熟悉Allegro/PADS Logic/CAM350/Orcad操作 ●工作流程 從PCB library零件建立,PCB Layout到 Gerber out *此工作非常適合熟悉或學習 Layout 作業* *非常適合擅於處理 PCB 板廠或PC板製程相關工作* *非常適合獨立執行作業與跨部門溝通之人才*
1. 依照硬體設計,完成產品的placement 和PCB佈線(熟多層板,盲埋孔layout) 2. 電子零件庫的建立與維護 3. 熟電子電路基本原理,能依據Design Guideline與設計者討論 4. 協助RD回覆PCB製作之相關工程問題 5. Layout Rule的規劃與制定
振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財,提供設計服務與硬體資安專利,保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境,歡迎您加入我們的團隊。 工作內容: • 負責IC版圖的自動佈局佈線、優化和驗證。 • 負責簡單電路的設計和模擬。 • 負責部分全定製版圖的設計和驗證。 • 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。 我們期望您具備的條件: • 大學以上;電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子相關科系畢業為主。 • 具相關工作經驗者為佳。 • 良好的團隊合作和溝通能力。 相關報導: 數位時代:陽明交大出身的Jmem Tek的硬體資安技術有何特別? https://meet.bnext.com.tw/articles/view/50065 DIGITIMES Asia報導:Chip startup JMEM TEK safeguards data security with hardware-software solution https://www.digitimes.com/news/a20221223VL202.html
1.對類比IC Layout 有興趣者, 英文或日文中等, 歡迎非本科系 2.無工作經驗可 3.相關科系.有英文或日文相關證照者佳
1. 負責 PC主機板/ IPC 主機板/ 平板主機板/ NoteBook主機板之 PCB Layout (使用 Cadance Allegro Placement,Routing,modify,Gerber out)設計 2. 對於 PCB 板廠製程及工廠SMT製程需有基本概念 3. 能夠完成Layout作業及團隊合作跟善於與人員做溝通協調
大塚是一家充滿活力、快速成長的公司,歡迎在這裡找到屬於自己的舞台! ●2008年10月股票掛牌上櫃 (股票代號3570) ●連續四年營收超越10億元 ●薪資水平在上櫃公司同業中名列前五名 ●擁有最完整的技術能量,每年客戶群超過2000家以上 ●是台灣產業涵蓋最廣的繪圖軟體解決方案代理商 ⭕ 工作內容 1. 熟悉電子硬體設計軟體,具電子產品開發經驗。 2. 提供客戶硬體設計與問題分析必要的技術支援。 3. 協助業務團隊推廣公司產品。 4. 具備良好溝通協調能力,主動積極,能獨立作業。 5. 配合專案執行,提供行銷建議、整理並製作技術文件。 ⭕ 需求條件 1. 具PCB Layout實務設計經驗5年以上 2. 熟悉PADS、PADS ROUTER、PADS LOGIC、Mentor產品軟體操作與應用 具備ORCAD、CAM350、ALLEGRO 尤佳 ⭕ 其他資訊 1. 薪資福利:依學、經歷面議核薪。 2. 上班時間:固定日班08:30-17:30 (含午休時間,彈性上下班30分)。 3. 依據公司經營狀況發放季獎金、年中分紅、年終獎金及員工酬勞等。
1.Layuot設計,PCB發包製作,SMT/DIP發包製作。 2.研究製作PCB產品相關分析與報告。 3.協助技術文件編寫。 Job Description 1.Layout design, PCB outsourcing and production, SMT/DIP outsourcing and production. 2.Research and create analyses and reports related to PCB product manufacturing. 3.Assist in the preparation of technical documents.
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.