4/26 數位IC設計工程師
- 鯨鏈科技股份有限公司
- IC設計相關業
- 台北市信義區
- 經歷不拘
- 碩士
1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. Digital front-end design flow
1. Architecture design, RTL coding, simulation, synthesis, LEC, STA 2. Digital front-end design flow
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.
1 prefer the experience of running SI/PI simulation tools such as ADS,Ansys, Hspice, etc. 2.with knowledge of transmission line, microwave and electric circuit theory BA degree in Engineering, Computer Sciences or equivalent.
【工作職責 (Responsibilities)】: ★ ARM series CPU integration ★ System bus architecture design and implementation 【Professional Experience】: ★ Experienced in ARM series CPU integration flow (ARM9, CA7, etc.) ★ Experienced in ARM cache, MMU, TCM design ★ Experienced in system bus architecture (AMBA AHB/AXI) design ★ Experienced in SoC chip integration 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ Outstanding problem analysis and debugging skills. ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool, member compiler 優秀條件 (Preferred Qualifications): ★ Nice to have experiences in scripting language. ★ Nice to have experiences in FPGA flow ★ Nice to have experiences in C language.
【工作職責 (Responsibilities)】: Work with a team to: ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ MS degree in Electrical Engineering, Computer Science or related field. ★ Proficient in Verilog coding and verification. ★ Experienced in front-end IC design flow. 優秀條件 (Preferred Qualifications): ★ Experienced in C language. ★ Experienced in scripting language. ★ Distinguished organizing abilities. ★ Outstanding problem analysis and debugging skills. ★ Optimistic and self-driven personality.
負責先進製程實體設計(APR in 5nm/7nm), 包含physical synthesis(DCG), floorplan, powerplan, placement, CTS, routing, timing fixing and DRC/LVS, . . ., etc. 1. APR hierarchical design flow. 2. Physical design project execution. 3. Responsible for physical verification including DRC, LVS and ESD checking. 4. Static timing analysis by using Synopsys PrimeTime. 5. Work Assignments. 6. Interdepartmental communication and collaboration.
1.從事FPGA RTL撰寫/設計 2.自有IP(Intellectual Property)設計/研發 3.特殊高端產品FPGA應用
1. 研究V2X與人機介面可能面臨之安全攻擊 2. 研究底層實體網路可能面臨之安全攻擊 3. 研究重要資料與軟體/韌體之可能安全漏洞 4. 針對車用所需網路安全提出防護機制 5. 實作關鍵防護機制之軟硬體
1.開發multi-mode GSM/WCDMA/LTE L1 software 2.開發OFDM信號處理嵌入式系統 3.開發ASIP/DSP架構數位通訊系統
【工作職責 (Responsibilities)】: ★ Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing ★ STA timing analysis and fixing ★ Physical verification, including DRC, LVS, IR drop and DFM analysis. ★ Physical design flow development and automation 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ 電機、資訊相關科系,學士或碩士畢業 ★ 具有獨立思考的能力,並習慣與團隊合作解決問題 ★ 高度的學習動機、願意投入精力分析和解決問題 優秀條件 (Preferred Qualifications): ★ 具有IC相關 tape out經驗 ★ 熟悉Tcl, Python語言
【工作職責 (Responsibilities)】: ★ Plan design architecture. ★ Develop high quality digital design. ★ Be familiar with IC design flow. ★ Professional Experience ★ Experienced in image/video module design ★ Experienced in SoC front-end integration flow ★ In-house core algorithms' module design 【符合條件 (Qualifications)】: 必須條件 (Minimum Qualifications): ★ Experienced in Verilog RTL language ★ Experienced in digital IC design front-end flow ★ Experienced in CAD tool usage such as simulation tool, linting tool, synthesis tool ★ Familiar with video codec algorithm (H.264, H.265, H.266, AV1)
1.USB3.0 host/device開發驗證相關工作 2.RTL coding/synthesis/simulation/verification
1.Deep algorithm knowhow in the field of camera/display/CV/AIAR. 2.Strong algorithm IP architecture design capability including early-stage cost analysis, data flow define, memory access scheme optimization. 3.Team work with algorithm team for fixed-point algorithm and cost reduction algorithm developing. 4.Familiar with SystemC to RTL flow is plus.
1. 負責系統晶片RTL整合,協助晶片bring-up,除錯與特性分析 2. 協助建立FPGA 3. 與Power團隊合作power分析與收斂 4. 與Physical design團隊合作Timing收斂與達成晶片面積目標 5. 與驗證團隊合作驗證,並建議測試計畫與驗證的方法 6. 根據規格,整合公司內部與外部IP 7. 與系統部門合作,了解系統與電路結構與系統需求 職務需求 1. 有工作經驗,並且與驗證團隊與Physical design團隊合作過尤佳 2. 了解有低功耗設計方法 3. 對RTL與產生的電路認識 4. 了解 bus結構,具備各種嵌入式記憶體知識,與晶片通訊界面規格 5. 了解reset與clock結構,具備Power domain設計知識 6. 了解專案資料庫版本管理系統 7. 了解Lint,DFT,UPF, 合成 8. 有Chip top的整合者經驗者尤佳
1.UVM verification environment build-up 2.Expert in SystemVerilog and constraint random. 3.Behavior model design from spec and verification proposal define. 4.Experience in formal verification is plus.
1.Ethernet IP設計及修改 2.RTL邏輯電路設計、驗證、合成 3.SoC IP設計、修改及整合 4.FPGA
【工作說明】 1. RISC-V coprocessor 架構設計 2. AI加速器架構設計 3. RTL實作 【必要條件】 1. 熟悉Computer Architecture like RISC-V, ARM, MIPS, etc. 2. 熟悉Verilog開發流程
1. SOC physical design implementation including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout etc. 2. Build physical design implementation flow for advanced process nodes including timing/power/DFM closure and CPU/GPU hardening. 3. Project leader and cross team project handling 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才,共創A+聯詠
1. SOC physical design implementation including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才,共創A+聯詠
我們專注於3D影像立體雙目視覺技術 產品應用於3D 影像辨識、360 度環景拍照、攝影或AR 與VR 職務內容: ★ USB2.0/3.1或 MIPI 介面之2D/ 3D 影像處理與壓縮之 IC 開發 ★ 影像處理與壓縮相關數位 IP暨產品之開發設計、測試、驗證 條件要求: 1. 對IP Verification, System Verification 有興趣 2. 熟Verilog coding 與 ASIC design Flow 與 Timing Closure 3. 或有 SoC IC 開發經驗