操作EDA軟體完成晶片實現, 包含 : •電路元件規劃擺放,佈局與繞線 (Floorplan, Place and Route) •時序收斂 (Timing closure) •壓降分析與收斂 (IR-drop analysis and fixing) •實體規則驗證 (DRC/LVS/ERC) •設計變更 (ECO) •EDA Tools: DesignCompiler/Genus, DFTCompiler, ICC2, Innouvs, Formality/LEC, PrimeTime, Calibre, Voltus, Redhaw
Job Title: NPU Modeling Engineer Job Description: Overview: We are seeking an experienced NPU Architect to join our team. As an NPU Architect, you will play a crucial role in designing and implementing the hardware model for our Neural Processing Unit. Your expertise will be instrumental in ensuring efficient and accurate execution of neural network workloads on our NPU. Responsibilities: 1. NPU Architecture Design: • Collaborate with cross-functional teams to define the architecture and specifications for the NPU. • Design the NPU's core components, including the PE array, memory hierarchy, and control logic. • Optimize for performance, power efficiency, and scalability. 2. Bit-True Hardware Model Implementation: • Develop a bit-true hardware model of the NPU in C language. • Ensure that the model accurately represents the NPU's behavior, including arithmetic operations, memory access, and control flow. • Validate the model against reference neural network workloads. 3. Cycle-Accurate Modeling: • Create a cycle-accurate model of the NPU to simulate its behavior at the clock cycle level. • Account for pipeline stages, data dependencies, and timing constraints. • Use tools like Verilog, system-Verilog, or specialized simulation environments to achieve cycle-accurate modeling. 4. Performance Analysis and Optimization: • Profile the NPU model to identify bottlenecks and areas for improvement. • Propose and implement optimizations to enhance performance and reduce latency. • Collaborate with software teams to fine-tune the NPU's behavior. 5. Verification and Validation: • Create testbenches and test vectors to validate both the bit-true and cycle-accurate models. • Conduct functional and performance testing to ensure correctness and compliance with specifications. • Debug and resolve any discrepancies between the models and the actual NPU. 6. Documentation and Communication: • Document the NPU architecture, design decisions, and implementation details. • Present findings, progress, and challenges to stakeholders and management. • Collaborate with software engineers, firmware developers, and system architects. Qualifications: • Master's or Ph.D. degree in Electrical Engineering, Computer Science, or a related field. • Minimum of 3 years of experience in NPU architecture design and implementation. • Proficiency in C/C++/Verilog/System-Verilog programming for hardware modeling. • Familiarity with systolic arrays, matrix multiplication, and neural network accelerators. • Knowledge of bit-true modeling, fixed-point arithmetic, and floating-point arithmetic. • Experience with verification tools and simulation environments. • Strong analytical and problem-solving skills. • Excellent communication and teamwork abilities. • Attention to detail and commitment to quality. If you are passionate about NPU architecture, hardware modeling, and want to be part of a team driving innovation, we encourage you to apply. Join us in shaping the future of AI!
擔任CAD (Physical Verification Design) 工作內容: 1.負責Command file撰寫與Maintain 2.Physical PG Sign-off Check 3.流程與程式開發 4. 需求條件: 4-1 工作經歷 : 2年以上，有先進製程(FinFET)經驗尤佳 4-2 擅長工具 : Calibre 、 ICV、TCL 4-3 工作技能 : DRC/LVS Command File撰寫 & 程式開發 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠
1. SOC 整合 2. AMBA APB/AHB/AXI與類比IP模塊控制等周邊電路 3. CPU wrapper 4. FPGA相關設計與實作 以上工作依個人意願酌情分配
1. 熟UVM等驗證。 2. 熟悉DDR、HDMI、USB、 SATA、PCIE、MIPI等IP設計驗證經驗者佳 3. 了解IC design flow.
1.Whole system signal and power integrity modeling and simulation including IP (DDR and other interface IP such as MIPI, PCIE, etc.), package and PCB. 2.Package and PCB model extraction for SI/PI simulation. 3.Co-work with IP designers to simulate and solve IP and system level SI/PI issues.
1 prefer the experience of running SI/PI simulation tools such as ADS,Ansys, Hspice, etc. 2.with knowledge of transmission line, microwave and electric circuit theory BA degree in Engineering, Computer Sciences or equivalent.
1. RTL Backend design tool and flow support - RTLA Floorplan tool and Innovus/ ICC APR flow support 2.Timing / Power / SI convergence flow for backend flow 3.IR / EM flow tool usage support
1. R2G flow in block level physical Implementation. 2. Library preparation & physical verification 3. Familiar with TCL/Shell/Programming.
* 電子/電機相關科系畢業 * 具DDR PHY 相關設計經驗佳 * 對DRAM系統，JEDEC spec有相對的理解 * Familiar with Spice simulation
NEUCHIPS is looking for skilled engineers for virtual prototyping of AI chips. Responsibilities: - Design virtual prototyping and architecture of SoC - Develop SystemC TLM models of AI accelerator - Analyze and optimize AI SoC architectures for performance and power Qualifications/Skills: - Understanding of C++/SystemC/Verilog - Familiarity with scripting (such as TCL, python, or Perl language) - Familiarity with AMBA protocol is a plus - Experience in IC development flow is a plus - Experience in virtual prototyping tools (e.g., Synopsys Platform Architect) is a plus Education and experiment requirements: - MS/Ph.D., Electrical Engineering or Computer Science
【產品線描述】 Smart TV Solutions：提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions：提供智能手機、智能電視、電競螢幕及商用顯示等產品各種ASIC解決方案 PD and Gaming Solutions：提供各種商用顯示及電競螢幕的控制晶片 【工作說明】 電視/手機相關晶片,影像視訊相關演算法品質調校： 1.研發建構品質調校軟體平台 2.手機遊戲畫質演算法改善與調整 3.新技術開發與探索 4.演算法品質調校,功能驗證與客戶問題應對 5.優化手機 AP (應用處理器)與畫質晶片流程控制 6.建立及優化 NPU (Neural Processor) 的 tool chain (SDK, UI, analysis tool) 【必要條件】 熟 C, C++程式設計
1. Discrete-time baseband behavior model of PA non-linear memory effect. 2. Measuring PA with created model to provide qualitative insight for PA performance tuning. 3. Digital signal processing for PA pre-distortion.
【產品線描述】 AMOLED, AR, VR, TDDI等面板驅動IC與觸控IC設計 【工作說明】 1.規劃建置DDIC系統數位DV (Design Verification)的UVM架構平台 2.建置驗證Model來優化信號驗證的效率 【必要條件】 1. 具系統DV (Design Verification) 建置能力 2. 熟悉UVM (Universal Verification Methodology) Flow, RAL (Register Abstraction Layer) model 3. 熟悉SystemVerilog, Verilog, C or C++, Python, Perl 4. 有使用Synopsys/Cadence VIP等相關經驗
1. 本區由身心障礙人才主動投遞履歷，我們將根據過去學經歷與專長進行媒合，如有合適職務，我們將主動與您聯繫. 2. 歡迎身心障礙人士應徵，需附身心障礙證明.
1. 熟悉Verilog HDL coding & simulation 2. 具馬達驅動控制相關經驗者佳，數位/混合信號IC設計相關經驗(論文或專題相關)
歡迎對加入成長中的團隊有興趣的工程師，除了高薪資收入以外，還可以參與了解到產品規劃的歷程，在清楚需求的壓力下，團隊一同努力達成目標，搶佔市場，獲得更好的收入和成就感。 如您具備以下經驗或興趣，歡迎與我們聯繫： 1.具eDP或 MIPI 或 小尺寸LCD Driver IC 或 TCON設計經驗。 2.具影像壓縮算法及電路設計經驗。 3.具MCU產品相關設計經驗。 4.具FPGA驗證經驗，熟悉軟硬体介面運作。
We are looking for people who can help and grow with our team. Neuchips is looking for a principal digital IC designer for SoC integration who can contribute organizationally of our AI solution to the world. Responsibilities: - AI accelerator design - Deep learning algorithm research - SoC integration - Design flow such as Linting, CDC, synthesis, logical equivalent checking, and STA - Performance, power, and area evaluation - EDA tools and design flow build-up - In-house automation tool/flow design Qualifications/Skills: - Familiarity with RTL coding and verification - Familiarity with scripting (such as TCL, python, or Perl language) - Familiarity with AMBA protocol - Experience in IC design flow is a plus - FPGA experience is a plus - Understanding of physical implementation/APR flow is a plus - Understanding of RISC-V is a plus - Low power design and UPF flow are preferred skills Education and experiment requirements: - MS/Ph.D., Electrical Engineering or Computer Science - A minimum of 3 years of digital IC design experience
【產品線描述】 Smart TV Solutions：提供TV SoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions：提供智能手機、智能電視、電競螢幕及商用顯示等產品各種ASIC解決方案 PD and Gaming Solutions：提供各種商用顯示及電競螢幕的控制晶片 【工作說明】 1. 整理客戶需求，規劃產品架構與應用情境。 2. 追蹤整理各項技術開發進展與客戶需求發展情況，製作文件，協助隊內與對外的會報與說明。 3. 了解產品相關演算法與規格，進行新技術survey，協助規劃產品發展方向。 【必要條件】 1. 具備面對客戶溝通與對內討論的意願 2. 具備演算法開發、或影像品質調校、或SoC數位電路設計、或技術專案管理的經驗
【產品線描述】 Evolution Video Display 新興顯示器開發： 1. Gaming monitor controller for LCD, OLED and Mini-LED. 專業電競螢幕，極致沉浸競界曲面螢幕，遊戲體驗身歷其境 2. Public display controller for LCD and Micro/Mini-LED. 大型商用顯示器，極窄邊框拼接電視牆，電子白板 3. Electronic Vehicle Display Controller. AR/2D HUD(抬頭顯示器)，車用高速顯示介面 4. Advanced Projector Controller. 低延遲的遊戲投影機、短焦投影機、浮空影像顯示器 5. 高階商用及電競顯示器整合方案ASIC晶片 6. USB4，USB 3.2，DisplayPort及PCI Express高速介面控制晶片 【工作說明】 1. 高速介面控制晶片設計 (a) USB4/USB 3.2 Host/Device/Hub Controller (b) PCI Express Device/Switch Controller 2. 高速介面數位設計驗證 (a) 建立高速介面自動化功能驗證環境 (b) 建立完整testbench以驗證功能及規格面之正確性 3. 高階製程 whole chip 及 IP 整合, DFT 及 low power 設計流程及驗證 4. FPGA驗證平台規劃與設計 【必要條件】 符合下列一或多項者 1. 高速數位介面USB, PCI Express, DisplayPort等Controller電路開發經驗 2. 熟悉systemverilog及UVM驗證架構。 3. Whole Chip整合，SoC IC設計流程實務經驗 4. 熟悉 Synthesis Tool, STA timing Analaysis Tool, TCL Language