5/04 VIS220181-Standard Cell Designer(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1. Standard cell library develop & maintain. 2. Cadence's & Synopsys's APR flow develop 3. Digital design flow consults
5/04 VIS230069-【2024研發替代役RDSS】佈局驗證工程師(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1.需求科系：碩士以上，(微)電子、電機、電物、資訊等相關系所畢。 2.班制：常日班。 3.工作內容： (1)製程開發平台之DRC/LVS/LPE開發維護 (2)新EDA應用流程及軟體(PERC/QRC/PVS)之程式開發維護 (3)協助客戶解決產品開發設計階段實體驗證以及驗證諮詢服務 4.說明： (1)請於履歷表中註明論文主題(方向)及所學專長。 (2)請檢附學士(含)以上之成績單。
5/04 VIS230076-【2024研發替代役RDSS】SRAM Memory Designer(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1.科系：碩士以上，理工相關系所(電子/電機系所,資訊工程所畢業尤佳)。 2.班制：常日班。 3.工作內容： (1)Responsible for SRAM Macro / SRAM Compiler Design. (2)SRAM Circuit Development; Verification and Maintenance 4.說明： (1)請於履歷表中註明論文主題(方向)及所學專長。 (2)請檢附學士(含)以上之成績單。
5/04 VIS220043-GPIO IP開發工程師(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 3年以上
- 大學
1. 負責GPIO 及客製化IO 開發與Test chip tape out 及驗證工作。 2. 協助客戶進行 IO 規格確認、使用與IP Qualification 品質項目服務。 3. 支援與協調GPIO設計、測試與電性分析等相關議題。
5/03 佈局工程師
- 昱盛電子股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 3年以上
- 專科
1. 具備基本 Linux操作能力 2. 具備 1~3年工作 IC layout經驗 3. 熟 Laker/Virtuoso 操作 4. 具備Analog或Mix-Signal產品 Layout經驗佳
5/03 CPU Synthesis Engineer
- 晶心科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 大學
Responsibilities Execute synthesis flow to report PPA for marketing promotion Enhance synthesis flow for reporting PPA Improve synthesis constraints Work with RTL designers to enhance dynamic power Qualifications Familiar with Verilog Have knowledge of power consumption Familiar with one programming language or one script language (e.g., C/PERL/Python /TCL) Good communicator in verbal and writing in English
待遇面議
員工370人
5/03 RD Team_Analog Layout Engineer_類比IC佈局工程師 (新竹)
- MPS_芯源系統有限公司
- IC設計相關業
- 新竹縣竹北市
- 2年以上
- 大學
Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Chip Planning • Project Schedule / Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Top Level connections • Signal matching / sensitive nets shielding technique • Chip power / ground planning • Integration of Analog top with Auto-Placement-Routing • Pad / ESD rule and routing / connection • Database DRC & LVS verifications on either DIVA or Dracula basis • Chip Tape-out in accordance with company’s Tape-out Procedure • Positive Attitude Qualifications: • 2+ years Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable
5/03 (NL30)IC Layout Engineer
- 新唐科技股份有限公司
- 其他半導體相關業
- 新竹縣竹北市
- 經歷不拘
- 大學
【本職缺僅接受新唐科技招募網站投遞】 請至新唐科技招募網站投遞個人履歷表，此職缺履歷登錄網址：https://jobs.nuvoton.com/ Create Test-key & standard cell Library & 客戶IP
待遇面議
員工1500人
5/03 IR Signoff/Codesign 工程師
- 聯發科技集團_達發科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 5年以上
- 大學
• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.
待遇面議
員工1100人
5/03 Analog IC Layout Engineer(年資3年以上)
- 新竹縣竹北市
- 3年以上
- 大學
1. Mixed mode 2. Analog layout / Chip integration 3. Full Customer Layout 4. 需support TF.、layer mapping file …
待遇面議
員工300人
5/03 電控課儲備幹部
- 金興精密工業股份有限公司
- 汽車及其零件製造業
- 桃園市平鎮區
- 經歷不拘
- 高中
1協助處理無刷/有刷電路板製程優化 2.協助排除生產狀況異常 3.參與產線優化規劃 4. 參與電控課相關作業及達標準管理 5.歡迎電子相關科系應屆畢業生 6.無經驗可
5/03 CAD技術副理
- 超炫科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 3年以上
- 碩士
1) Build up the IC design flow. 2) Including Library preparation, floorplan, power plan, CTS, timing closure, PV. 3) Familiar with Tcl/Shell/Perl/makefile. 4) Interesting in IC design backend cad flow creation
待遇面議
員工40人
5/02 Staff Analog Layout Engineer
- Marvell_邁威爾科技有限公司
- IC設計相關業
- 新竹縣竹北市
- 4年以上
- 大學
Job Responsibilities: You will be working with global teams in Argentina, Singapore, the U.S., and throughout Europe. You’ll receive a schematic from an Analog IC Designer. You will then take that schematic and use a CAD tool to graphically design the layers of that schematic. Then, you run simulations and verifications on the design using Cadence Virtuoso, refine and debug as needed in concert with the designer, and both of you keep iterating the design until it meets the desired specifications. Each project can last from a couple of months to a year and a half. You will likely work on just one project in that time but may be asked to switch to something else if priorities change. Your flexibility is appreciated. You’ll meet every few days with the designer you’re paired with to share information and work together. No circuits get built or tested here without you both, so your partnership and teamwork are extremely valuable to Marvell. You’ll also have routine meetings with your technical mentor when you have questions, as well as the layout team and the project team where you may have to speak to the entire group and update them about your progress. You may have to present a particular issue or solution you’ve encountered. We are developing brand new cutting-edge technologies here, so we learn new things frequently and share them with our colleagues.
5/02 【實習生】Intern, Analog Layout
- Marvell_邁威爾科技有限公司
- IC設計相關業
- 新竹縣竹北市
- 經歷不拘
- 碩士
C佈局工程師 1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 負責簡單電路的設計和仿真。 3. 負責部分全定製版圖的設計和驗證。 4. 負責CMOS Sensor規格訂定，系統驗證及Demo Board設計。 5. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。
待遇面議
外商公司
5/02 VLSI Physical Design Manager/Designer (KW: APR, P&R)
- 安霸股份有限公司
- IC設計相關業
- 新竹市
- 2年以上
- 碩士
1.VLSI Physical Design 2.Executing floorplanning, design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3.Tapeout with multi-million gates count SOC design on leading edge technologies. 4.Develop physical design flows/solutions on the latest cutting edge technology node.
待遇面議
員工240人
5/02 【新竹】IC實體設計工程師
- 晶密股份有限公司
- 電腦軟體服務業
- 新竹縣竹北市
- 2年以上
- 大學
1. Deal with all aspects from gate level netlist to GDS. 2. Implementation with emphasis on floorplan, clock tree synthesis, place and route, STA, power analysis. 3. Sign-off verification of block/whole chip level physical implementation with QoR (power/performance/area) consideration. 4. Checking and fixing of DRC, LVS. Antenna.
待遇面議
員工50人