5/02 IC Layout Engineer
- 兆發科技股份有限公司
- 其他電子零組件相關業
- 新竹市
- 經歷不拘
- 專科
1. 具學習 IC Layout 學習熱忱 (無經驗可)。 2. Layout Tool的運用&學習(Virtuoso , Laker, calibre...)。 3.可接受出差。
5/02 [新竹]2024 三星電子未來之星Internship Program -Power IC Designer
- 台灣三星電子股份有限公司
- 半導體製造業
- 新竹縣竹北市
- 經歷不拘
- 碩士
(1) 閱讀及報告下列主題的論文: DVS, fast load/line transient, SIMO控制架構等 (2) 訓練子電路設計流程及相關模擬檢查 ※ Internship Period: Jun 24, 2024~ Aug 30, 2024 (實習期間有機會至韓國總部參訪學習)
5/02 類比設計工程師
- 威達高科股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 大學
1. 有下列任一領域設計經驗: (大學專案或論文曾涉略過亦可) a. Power Generator b. Clock Generator c. Analog Front End 2. IC測試、驗證與偵錯 3. 針對無工作經驗之畢業生，本公司備有新進工程師培訓計畫
待遇面議
5/02 [新竹]Display Driver IC Analog Designer(大尺寸)
- 台灣三星電子股份有限公司
- 半導體製造業
- 新竹縣竹北市
- 經歷不拘
- 碩士
-Objective, mission a. Familiar with analog circuit design and Mass production experience, like Bandgap reference, OPAMP, Receiver, DAC, ADC, Level shifter, … etc.. b. LCD driver circuit design experience is a plus. -Main responsibilities Display Driver IC Analog Block Design and Whole Chip Handling for TV Panel -Daily works Co-work with colleagues to design a DDI chip. On-time deliver for requested jobs is must.Communicate with HQ and related development departments for high quality product. -Customer LCD Module Maker
5/02 [暑期實習生] RF硬體實習生
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 大學
職務說明： 1. 安排熟悉RF SOC 或 RF Transceiver 之晶片規格及開發環境 2. 協助RF PCB 設計以及RF特性驗證 3. 協助自動化測試環境建立 4. 協助Application Note撰寫 工作技能： 需具備RF電路、PCB 設計或天線等相關知識 具基本無線通訊知識尤佳
5/02 【研發替代役】數位/類比IC設計工程師 (無線應用)
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1. 電路設計及產品偵錯。 2. 請備妥自傳. 大學及研究所成績單. 論文摘要等資料。
5/02 類比IC設計工程師(sensor感測器)
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 3年以上
- 碩士
1. High precision, low-noise Analog front-end產品開發設計. 2. 熟悉類比周邊電路設計 (current bias, LDO, bandgap, buffer, etc.) 3. High resolution sigma-delta converter設計經驗. 4. Class A/AB/D opamp circuit design. 5. 協助整合晶片functional block.
5/02 類比IC設計工程師(音訊/電源)
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 2年以上
- 碩士
1. 電視及手機應用的 Audio IC相關晶片類比電路之開發。 2. 熟類比電路者。 3.熟悉Audio或電源管理IC應用與測試條件。 4.電源管理IC之規格及開發時程評估。 5.電源管理IC之IP電路開發、整合。 6.電源管理IC 之驗證及驗證問題解決。 7.電源管理IC 之量產前故障問題之分析。 8.提供電源管理IC 客訴時之專家意見。
5/02 類比IC設計工程師
- 金麗科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 碩士
1. High Speed SerDes circuit Design 2. Receiver 3. Transmitter 4. CDR 5. CTLE 6. PLL
5/02 DRAM IC設計工程師
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1. DRAM Circuit Design/Simulation 2. High Speed I/O Design/Simulation 3. Layout Verification 4. 能獨立思考, 解決問題
5/02 【研發替代役】類比IC設計工程師(音訊/電源)
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1. 電視及手機應用的 Audio IC相關晶片類比電路之開發。 2. 熟類比電路者。 3.熟悉Audio或電源管理IC應用與測試條件。 4.Audio/電源管理IC之規格及開發時程評估。 5.Audio/電源管理IC之IP電路開發、整合。 6.Audio/電源管理IC 之驗證及驗證問題解決。 7.Audio/電源管理IC 之量產前故障問題之分析。 8.提供Audio/電源管理IC 客訴時之專家意見。 9. 請備妥自傳. 大學及研究所成績單. 論文摘要等資料。
5/02 類比IC設計工程師(無線應用)
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 5年以上
- 大學
1. Design wireless SoC analogue building blocks 2. Review design specification based on system requirements. 3. Communicate with baseband algorithm, RF system, device and layout teams. 4. Present topology studies, design consideration, simulation and verification plan. 5. Conduct lab measurement and report design-vs- silicon correlation. 6. Experience with any of the below is a plus •Wireless SoC development •LNA •Mixer •Amplifier •VCO •PLL •Baseband Filter •VGA •ADC •PMU •LDO •oscillator
5/02 類比設計研發主管
- 威達高科股份有限公司
- IC設計相關業
- 新竹市
- 10年以上
- 碩士
1. 有下列領域設計經驗 : a. Power Generator b. Clock Generator c. Analog Front End。 2. IC 整合與ESD相關經驗。 3. IC 測試、驗證與偵錯。 4. 計劃/部門工作規劃、分配、輔導與管理。
待遇面議
5/02 【實習】Intern-Spice Model Intern (Hsinchu)(3060447)
- 新竹市
- 經歷不拘
- 碩士
Job Description This opening is for an intern, who will be working with a Spice Model Group located in San Diego USA & Taiwan, utilizing Spice Models for state-of-the art CMOS to RFA Circuit interaction for device KPI vs. circuit performance, working with leading edge semiconductor foundries, to meet Qualcomm's advanced product roadmap requirements in Digital, RF, PMIC, Mobile, Connectivity, Automotive, IOT, and Artificial Intelligence, etc. Candidate will be working with the San Diego & Taiwan Spice Modeling, Process/Device, DevLab Teams on simple circuit design simulation for technology benchmark evaluation, Investigation on simulation correlation study between device/transistor characteristic and RFA circuit performance. Test structure layout design for Si characterization from benchmark circuit across foundries. Goals: • Working with circuit design team / Spice model team / process device team to design simple analog/rf circuits in deep sub-micron CMOS technologies for technology assessment. • Running complete set of design verification tools on analog/rf circuit and correlation analysis to transistor device characteristics. • Utilizing CAD layout tool and interpreting LVS, DRC reports to find the fastest way for test-chip layout design work. Internship requirement: • M.S. or Ph.D. candidate (final year preferred), majoring in Electrical engineering or Physics. A good understanding of semiconductor device physics and basic circuit design operation is a plus. • Hands-on fundamental building block design experience. • Solid understanding of CMOS process and device characteristics, and scaling-related impact to circuit design. • Familiar with one of the following programming/scripting languages: Python, C or Perl, familiar with html is a plus. • Self-motivated, fast learner, hard-working and good teamwork skills. • Good English speaking, and written communication skills
待遇面議
外商公司
5/02 Custom Circuit Characterization and Modeling Engineer (Hsinchu) (3059130)
- 新竹市
- 3年以上
- 大學
The candidate will be responsible for developing advanced modeling formats for memory / std cell/ IO IP through application of circuit design knowledge, characterization methodology, data analysis and visualization & large-scale software automation enablement. You will be doing as following: - Define and implement standard cell, memory and IO characterization methodology for leading edge technology. - Path finding and innovation of new cell and/or new feature characterization. - Develop flows to meet advanced tech node requirements using Perl/Python/tcl - Have creative new insights to support existing tools and flows and develop new simulations to perform timing/power/noise/OCV evaluations. - Collaborate with cross function teams with regards to library and frontend issues related to IP - Work closely with EDA vendors on latest tool feature development and qualification Minimum Qualifications - Bachelor's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience; or, - Master's degree in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience; or, - PhD in Science, Engineering, or related field.
待遇面議
外商公司
5/02 《AD-08》高壓元件設計工程師
- 義隆電子股份有限公司
- 半導體製造業
- 新竹縣寶山鄉
- 1年以上
- 碩士
1. 高壓元件(MOSFET、IGBT、GaN、SiC) 或 HV Protect ESD 設計開發 2. 高壓元件及ESD 電性量測收集與FA 分析 3. 支援類比電路 AIP 設計維護
5/02 [暑期實習生] 音訊與電源IC實習生
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 大學
職務說明： 1. 研讀音訊與電源相關技術文件, 如論文, 專利, IC 規格書 2. 電路優化與組建電路，並達到指定的功能要求 3. IC 量測 工作技能： 需熟悉 Hspice, Laker
5/02 聲學系統應用工程師(需外派日本)
- 律芯科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 專科
1. 演算法驗證 2. 音頻儀器操作 3. System level trouble-shooting 4. IC/FPGA verification 5. 搭配產品應用端需求修正相關設計參數 **此職務需外派日本與客戶直接溝通，外派時間未定，有長期外派可能(6個月以上)
待遇面議
5/02 [暑期實習生] 感應器實習生
- 晶豪科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 大學
職務說明： 1.使用自行開發的MCU做消費電子產品及智能家電的韌體方案開發 2.針對所開發的方案，做完整的文件紀錄並撰寫Application Note 3.安排熟悉MCU電氣規格及開發環境 4.指派1~2個應用方案，完成韌體程式撰寫，並達到指定的功能要求 工作技能： 需熟悉C語言，組合語言、Keil IDE環境、電子電路及信號處理
5/02 IO/Verilog Characterization and Modeling Engineer (Hsinchu) (3060881)
- 新竹市
- 4年以上
- 大學
This is a Verilog modeling and characterization engineer position in Methodology, Flow and Design Kit team involved in defining methodologies, flows and in delivering design kit including behavioral models and timing models for I/Os, memories and standard cell libraries in state of art CMOS/FinFET technology nodes for Qualcomm's advanced mobile baseband, Auto, IOE/IOT & consumer products. Job Responsibilities - Write RTL models in Verilog for the different flavors of IOs. - Build verification plan and verify the design including both behavioral models and transistor level implementation. - Experience in System Verilog assertions(SVA), Power aware verification and formal verification is necessary. - Debug issues at IP level and SoC level. - Prior experience in analog/mixed signal simulations is preferred. - Solid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected. - Understand the I/O circuit architecture and write stimulus for Timing/Power characterization. - Need to be familiar with various Liberty models including NLDM, CCS, LVF. - Work with internal customers to understand the requirements and support the SoC team on behavioral models and timing models throughout the design cycle. - Exposure to RTL to GDSII flow is required. Understanding of STA and exposure to the flow is necessary. - Interaction with tool vendors to drive the flow improvements and methodologies to address the requirements from latest technologies - Solid understanding of VLSI circuits and Spice simulator experience along with commercial characterization tool experience is expected. - Drive and build automation with any of the scripting languages like Python/Perl/TCL to improve the productivity and quality. - Responsible for developing new methodologies and flows to support complex designs, driving the design verification reviews, automation and drive productivity & quality.
待遇面議
外商公司