5/04 VIS220181-Standard Cell Designer(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1. Standard cell library develop & maintain. 2. Cadence's & Synopsys's APR flow develop 3. Digital design flow consults
5/04 VIS220048-SRAM Memory Designer(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1.Responsible for SRAM Macro / SRAM Compiler Design. 2.SRAM Circuit Development; Verification and Maintenance
5/04 VIS220057-IC Memory Designer(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1.負責 eFuse IP 與 eFuse Testchip 之設計開發; IP Design kits 產出與 Silicon驗證工作. 2.負責 OTP (One-Time-Program) IP 與 OTP Testchip之設計開發; IP Design kits 產出與 Silicon驗證工作. 3.負責 MTP (Multi-Times-Program) IP 與 MTP Testchip之設計開發; IP Design kits 產出與 Silicon驗證工作. 4.熟悉類比電路設計, eg: Charge Pumping; Bangap Reference; DLL; MBIST; ECC…等 Functional Blocks.
5/04 VIS240026-【2024年研發替代役】Foundation IP Designer （新竹廠）
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1.科系：碩士以上，理工相關系所(電子/電機系所,資訊/資管工程所畢業尤佳)。 2.班制：常日班。 3.工作內容： 3.1 Standard Cell design team: -Standard cell電路設計。 -Standard cell characterization and PPA分析。 3.2 GPIO design team: -GPIO (General-Purpose Input/Output) 電路設計及ESD/Latch-up 驗證。 -支援與協調GPIO設計、測試與電性分析等相關議題。 3.3 SRAM/ROM design team: -SRAM Macro / SRAM Compiler設計, 驗證及維護。 -ROM Macro / ROM Compiler設計, 驗證及維護。 3.4 IP-CAD design team: -Design kit flow and IP QC flow建立和維護。 -Test chip development includes design, APR and verification。 3.5 熟悉類比電路設計尤佳, eg: opamp; Bangap Reference; PLL/DLL…等 Functional Blocks. 3.6 熟悉數位電路設計尤佳, eg: DFT; MBIST; ECC…等 Functional Blocks. 3.7 熟悉程式語言設計尤佳, eg: Python; TCL…等。 備註：主管將依照專才分發至不同 design team。
5/04 VIS220043-GPIO IP開發工程師(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 3年以上
- 大學
1. 負責GPIO 及客製化IO 開發與Test chip tape out 及驗證工作。 2. 協助客戶進行 IO 規格確認、使用與IP Qualification 品質項目服務。 3. 支援與協調GPIO設計、測試與電性分析等相關議題。
5/03 Memory IP Design Engineer
- 美商朗格股份有限公司台灣分公司
- 其他商品批發業
- 新竹市
- 3年以上
- 大學
Applicant will have Test, design and verification responsibilities for Allegro's internally developed custom memories including SRAM, ROM, One-Time-Programmable, and EEPROM. Responsibilities: - Transistor-level circuit design, simulation, and testing. - Create test/validation plan for different sizes of memories. - Documentation/application note development and customer support. Job Requirements: BSEE or MSEE with 2+ years' experience with memory design, circuit simulation and testing; knowledge of transistor level circuit design and layout; knowledge of CMOS fabrication methods and digital circuits; experience with layout parasitic extraction and simulation tools; strong written and verbal communication skills; experience with Unix shell languages; understanding of issues and modeling of variation in deep sub-micron technologies; knowledge of verilog modeling; familiarity with layout verification tools, design rules, and rule decks.
待遇面議
5/03 CPU Synthesis Engineer
- 晶心科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 大學
Responsibilities Execute synthesis flow to report PPA for marketing promotion Enhance synthesis flow for reporting PPA Improve synthesis constraints Work with RTL designers to enhance dynamic power Qualifications Familiar with Verilog Have knowledge of power consumption Familiar with one programming language or one script language (e.g., C/PERL/Python /TCL) Good communicator in verbal and writing in English
待遇面議
員工370人
5/03 【派駐聯發科/新竹U】CAD engineer – APR/IR drop analysis/AL
- 就業情報資訊股份有限公司
- 人力仲介代徵
- 新竹市
- 經歷不拘
- 大學
1. IRdrop execution for IR sign-off flow regression. 2. Utility maintenance of APR placement rule 3. 提供3個月Internal training，並有on-job training with mentor 4. 工作細節請參照下方工作內容參考URL # https://www.youtube.com/watch?v=LMDiRO9QNtE ( What is Physical design 英文影片) # https://www.youtube.com/watch?v=9QvK6083no8 (IR drop analysis flow英文影片)
5/03 Principal Semiconductor Wafer Technology R&D Engineer
- 美商朗格股份有限公司台灣分公司
- 其他商品批發業
- 新竹市
- 10年以上
- 大學
For this position, primary responsibilities will be Technology Transfer and Yield Ramp support for Allegro production BiCMOS, BCD, Sensor, and High Voltage technologies, Allegro emerging technologies and technology transfers to foundry locations world-wide. As part of the Wafer Technology R&D Foundry team you will work with Allegro wafer manufacturing partners to meet Allegro’s Technology and Manufacturing Road Map. Your responsibilities will include: • Technology transfer to leading semiconductor foundries. • Transferring, developing, integrating and sustaining processes in a semiconductor fabrication facility. • Developing and sustaining robust Deep Trench Isolation (DTI) and Epi production processes for technology transfer. • Design of Experiments, Smart transfer methodology, process qualification, troubleshooting problems, supporting risk-production and yield ramp programs, cost and cycle time improvements, characterizing and releasing process improvements. • Working with Semiconductor foundry to leverage existing processes and equipment for technology transfers. • Match WAT, Device Models, Product yields, Wafer Level Reliability, and performance to parent Fab. • Lead Tiger Teams to manage Yield Ramps. Qualifications: • BS, MS or PhD in Chemical Engineering, Material Science Engineering, Electrical Engineering, or related field with experience in semiconductor fabrication. • 10+ years-experience preferred. • Strong knowledge of unit process, process integration and wafer manufacturing flow. • Good knowledge of Semiconductor device Physics, TCAD experience is a plus. • Good team player with excellent communication in English & Mandarin. Cross functional problem solving, and statistical analysis skills are required. • Proficiency expected in design of experiments, statistical process control, and data analysis software and automated report generation. • Knowledge of fab metrology equipment, failure analysis techniques and process control techniques is required. • Understanding circuits and circuit design; circuit design experience is a plus. • Applicant will be a self-starter who is capable of driving technology transfer and meeting Advanced Quality Planning (AQP) project schedules & milestones.
待遇面議
5/03 數位 IC 設計工程師 I
- 佑華微電子股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 碩士
1. 數位電路設計、模擬與驗證 2. AMBA(AHB/APB)與IP整合 3.微控制器、微處理器架構設計 4.Audio/Speech相關演算法開發與設計 5.協助開發與驗證FPGA電路 6.RTL Synthesis , Design Timing Constraint 7.POR、BOR、LVR、IO PAD、PWM、Level-shifter、SRAM、ADPLL設計(SPICE simulation)
待遇面議
上市上櫃
5/03 演算法應用工程師(I1)
- 聯詠科技股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
【產品線描述】 Smart TV Solutions：提供TVSoC、MEMC/FRC及面板相關顯示裝置的控制晶片 ASIC Solutions：提供智能手機、智能電視、電競螢幕及商用顯示等產品各種ASIC解決方案 PD and Gaming Solutions：提供各種商用顯示及電競螢幕的控制晶片 【工作說明】 電視/手機相關晶片,影像視訊相關演算法品質調校： 1.研發建構品質調校軟體平台 2.手機遊戲畫質演算法改善與調整 3.新技術開發與探索 4.演算法品質調校,功能驗證與客戶問題應對 5.優化手機 AP (應用處理器)與畫質晶片流程控制 6.建立及優化 NPU (Neural Processor) 的 tool chain (SDK, UI, analysis tool) 【必要條件】 熟 C, C++程式設計
5/03 SoC Performance Architect
- 創鑫智慧股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 碩士
NEUCHIPS is looking for skilled engineers for virtual prototyping of AI chips. Responsibilities: - Design virtual prototyping and architecture of SoC - Develop SystemC TLM models of AI accelerator - Analyze and optimize AI SoC architectures for performance and power Qualifications/Skills: - Understanding of C++/SystemC/Verilog - Familiarity with scripting (such as TCL, python, or Perl language) - Familiarity with AMBA protocol is a plus - Experience in IC development flow is a plus - Experience in virtual prototyping tools (e.g., Synopsys Platform Architect) is a plus Education and experiment requirements: - MS/Ph.D., Electrical Engineering or Computer Science
待遇面議
遠端工作
5/03 【新竹】Physical Design Engineer
- 聯詠科技股份有限公司
- 半導體製造業
- 新竹縣竹北市
- 經歷不拘
- 碩士
1. SOC physical design implementation including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠
5/03 Digital IC Design/Verification engineer 數位 IC 設計/驗証工程師
- 英屬開曼群島商世芯股份有限公司台灣分公司
- IC設計相關業
- 新竹縣竹北市
- 2年以上
- 大學
1. DDR/PCIe/UCIe configuration, integration and verification. 2. Interact with external IP vendors/customers to resolve integration /implementation issues. 3. Co-work with customers for chip bring-up.
待遇面議
員工500人
5/03 <身心障礙媒合專區>
- 佑華微電子股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 高中
1. 本區由身心障礙人才主動投遞履歷，我們將根據過去學經歷與專長進行媒合，如有合適職務，我們將主動與您聯繫. 2. 歡迎身心障礙人士應徵，需附身心障礙證明.
待遇面議
上市上櫃
5/03 (CW10)Digital IC engineer
- 新唐科技股份有限公司
- 其他半導體相關業
- 新竹縣竹北市
- 2年以上
- 大學
【本職缺僅接受新唐科技招募網站投遞】 請至新唐科技招募網站投遞個人履歷表，此職缺履歷登錄網址：https://jobs.nuvoton.com/ 1. Digital IP developing, digital circuit design & design verification 2. Architecture design & integration (MCU) 3. Front-end: RTL coding, simulation, lint 4. Experience for communication IC developement is a plus 5. Familiar with FPGA development flow is required 6. Nice to have experience of digital signal processing
待遇面議
員工1500人
5/03 數位設計驗證工程師
- 聯發科技集團_達發科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 碩士
Develop and maintain environment for SOC pre-silicon verification of: • RTL and netlist simulation • CRV for system fabric • Power-aware simulation • Formal CC and FPV • System level verification with SVA
待遇面議
員工1100人
5/03 【2024暑期實習】Physical Design工程師
- 聯詠科技股份有限公司
- 半導體製造業
- 新竹縣竹北市
- 經歷不拘
- 碩士
聯詠科技2024暑期實習計畫，提供您貢獻所學、學習成長的實習平台與成長機會。 誠摯歡迎您加入我們，和聯詠一起並肩打造智慧影像影響全視界！ ●上班時間為週一至週五8:30-17:30，週休二日。 ●實習計畫可配指導教授會議，依規定請假。 ●每位實習生有專屬指導者共同參與專案性工作。 ●實習地點於新竹，外地同學享住宿補助。 ●實習期間表現優秀者，可優先參與聯詠正職預聘計畫。 ●申請條件： 1. 碩博班等電資學院相關系所在學學生(含預碩生)。 2. 應徵前，請先徵得指導教授同意參與暑期實習。 3. 實習期間：2024暑期 (視各校本學期結束與下學期開學的期程而定)。 4. 投遞104人力銀行暑期實習生職缺，於自傳中說明論文或專題研究方向，並檢附成績單。預碩生請於學歷欄註明碩士學歷。 ●工作內容： 1. APR physical design, including floorplan, power plan, physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR physical design methodology development & automation ●需求條件： 1. 修課包含VLSI相關課程, 具備邏輯電路基本觀念 2. 曾修習VLSI lab 或TSRI(原CIC)課程Cell-Based IC Physical Design with SOC Encounter(IC Compiler)等流程實作尤佳 3. 研究領域為EDA相關尤佳
5/03 數位IC設計工程師
- 新竹市
- 經歷不拘
- 碩士
1. 負責MCU/DSP開發 2. Embedded/SoC chip integration(floorplan design, package bonding, whole chip synthesis) 3. FPGA integration
待遇面議
5/03 數位IC設計工程師
- 超炫科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 經歷不拘
- 大學
1. Driver IC 設計 2. TCON IC 設計 3. 高速介面電路設計 4. 依照演算法開發設計數位電路，以達到系統的要求。
待遇面議
員工40人