C佈局工程師 1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 負責簡單電路的設計和仿真。 3. 負責部分全定製版圖的設計和驗證。 4. 負責CMOS Sensor規格訂定，系統驗證及Demo Board設計。 5. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。
General Summary: - Enabling automation system and flows with multiple languages like Perl/Python, skill, SVRF& tcl - Development of Back end tools and APIs - Development of Dashboards using data processing tools and front end HTML - Cross domain automation projects with multiple functional teams like circuit design, Layout and characterization teams. Basic Qualifications: - 2-6 years of experience in layouts and CAD automation - Knowledges in SVRF or SKILL coding - Hands-on experience in script languages such as Perl, Python & shell - Experience in industry standard layout and verification tools (Preferred) - Experience in the standard cell domain (Preferred) - Good understanding of CMOS circuit design fundamentals (Preferred) - Communication skills and ability to work across multiple projects Preferred Qualifications: - Knowledge of scripting language is mandatory (Proficient in PERL/Python & SHELL scripting) TCL, and Svrf Scripting is needed. - Good Programming skills and hands on experience in Perl, Python , shell and tcl languages. - SVRF coding of rule decks and or modifying existing rules/SVRF for manipulating layout views. - Experience in EDA tool/flow/methodology, product and IP developments. - Understanding of Layouts and qualification methodologies - Familiarity with Layout tools like virtuoso and calibre, Simulators (HSPICE, FineSim), understanding of schematics, netlist syntax and other Validation tools. - Strong communication and interpersonal skills to champion initiatives internally and externally. - Programming expertise in html to develop dashboards and webpages is an additional plus.
Job Responsibilities: You will be working with global teams in Argentina, Singapore, the U.S., and throughout Europe. You’ll receive a schematic from an Analog IC Designer. You will then take that schematic and use a CAD tool to graphically design the layers of that schematic. Then, you run simulations and verifications on the design using Cadence Virtuoso, refine and debug as needed in concert with the designer, and both of you keep iterating the design until it meets the desired specifications. Each project can last from a couple of months to a year and a half. You will likely work on just one project in that time but may be asked to switch to something else if priorities change. Your flexibility is appreciated. You’ll meet every few days with the designer you’re paired with to share information and work together. No circuits get built or tested here without you both, so your partnership and teamwork are extremely valuable to Marvell. You’ll also have routine meetings with your technical mentor when you have questions, as well as the layout team and the project team where you may have to speak to the entire group and update them about your progress. You may have to present a particular issue or solution you’ve encountered. We are developing brand new cutting-edge technologies here, so we learn new things frequently and share them with our colleagues.
1.VLSI Physical Design 2.Executing floorplanning, design closures on timing, signal integrity, power integrity, DFM as well as physical verifications. 3.Tapeout with multi-million gates count SOC design on leading edge technologies. 4.Develop physical design flows/solutions on the latest cutting edge technology node.
1. 具學習 IC Layout 學習熱忱 (無經驗可)。 2. Layout Tool的運用&學習(Virtuoso , Laker, calibre...)。 3.可接受出差。
1. Responsible for ASIC physical implementation by using automatic place and route tools . The P&R processes including floorplan, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimization. 2. Responsible for physical verification including DRC, LVS and ESD checking.
1. 負責產品之佈局、DRC、LVS， 並產生供光罩製作之data base。 2. 具IC佈局相關工作經驗，須了解製程與ESD、Latch up。 3. 熟悉 Laker, Calibre.
• Participate in sub-blocks and module-blocks floor planning and routing from scratch. • Perform layout blocks verification with sign-off in area (such as DRC, LVS, ANT, ERC & PERC) and troubleshooting the results. • Good hands-on experience in analog layout device matching techniques, high speed shielding and validation, as well to have acquired broader knowledge in handling high voltage devices. • Co-work with architect, design lead, designers, layout lead and layout engineers to achieve modules/full chip integration, place and route, chip level verification and tape-out. • Responsible for layout optimization, post layout extraction and parasitic analysis by ensuring analog and mixed signals circuits meet chip level tape-out, sign-off at desired area, performance, and power. • Specific technical expertise is desired in a broad range of process technologies from Bipolar, CMOS, DMOS (BCD) to FinFET advance node in complex, high-performance analog and mixed signals circuits layout. • Proactively look for continuous improvement opportunities in the complete layout flow methodologies (flow, layout, and design) as well as develop accurate IC layout design schedules and resource estimates.
1. Deal with all aspects from gate level netlist to GDS. 2. Implementation with emphasis on floorplan, clock tree synthesis, place and route, STA, power analysis. 3. Sign-off verification of block/whole chip level physical implementation with QoR (power/performance/area) consideration. 4. Checking and fixing of DRC, LVS. Antenna.
1. High Speed SerDes circuit Design 2. Receiver 3. Transmitter 4. CDR 5. CTLE 6. PLL
The IC Package System Design Team at Qualcomm has an opening for Package/System Design Engineer. This team is responsible for road mapping, architecting, design methodology, design implementation and verification for all Qualcomm package products (Digital, RF, Analog, PMIC, etc...). Job responsibilities for this position include package selection, package design, and package EE modeling. This involves optimizing system co-design of IC-PKG-PCB die keeping in mind package footprint/height constraints, IC floor-planning, PCB, high-speed signal integrity, power distribution network, and thermal constraints. Additional responsibilities: IC top level floorplanning including hard macro block placement, padring, RDL and bump pattern/assignment System level co-design methodology of IC, Package and PCB/Board Concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve lowest system level cost Package design flow methodology implementing high speed interface SI constraints for jitter, IR drop, cross-talk, and SSN specs Package design flow methodology implementing power distribution network (PDN) constraints for high speed processor cores (1GHz+) including design optimization techniques at the die/pkg/PCB levels Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products
1. 有wholechip經驗，能獨立且佈局符合circuit designer設計需求 2.Layout tool 操作熟悉( Laker OA,Laker3,Calibre DRC/LVS check) 3.有TSMC,UMC,HHGrace相關製程經驗 4.有高壓或Analog IC layout經驗
Becoming part of the creator of ultra-high speed interconnect technology to enable the next generation of Cloud Data Centers, you have the chance to create the technical differentiation for eTopus to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Roles & Responsibilities: 1. Perform daily layout editing, DRC/LVS tasks to ensure the quality of the layout. 2. Work close with circuit designers to optimize the floor plan. 3. Create a solid power grid for better power integrity. 4. Work with the circuit designers to optimize the quality of the layout, including but not limited to matching and signal integrity. Qualification/Experience/Skills Required: 1. Familiar with layout editing tools, such as Cadence Virtuoso, Synopsys Custom Compiler, Synopsys Laker, etc.. 2. Proficient with DRC/LVS/ERC verification tools and flows, such as Calibre, PVS or ICV. 3. Have extensive experience designing layout in deep sub-micron CMOS technologies, especially FinFET technologies. 4. Decent understanding in the issues of electro-migration and IR drop, RC delay, self-heating, capacitive cross-talk, etc. 5. Decent understanding in analog layout requirements, such as matching and shielding.
1. Mixed Mode IC Layout, 解決DRC/LVS. 2. 能與Analog Design Team密切溝通合作，調整layout到最佳化. 3. 具先進製程FINFET N16 N12 N7 N5 process IC layout 相關經驗. 4. 具有經驗解決EM 或 IR drop, RC delay, capacitive cross-talk. 5. 具高速電路layout 相關經驗.
IC Analog / Digital Full Layout Whole chip integration
(1)BS degree in EE of related experience. (2)Familiar with IC design flow and DFT.
1. sub-block layout. 2.channel layout. 3.whole chip IC layout.