5/03 【台南】IC佈局工程師
- 聯詠科技股份有限公司
- 半導體製造業
- 台南市永康區
- 經歷不拘
- 大學
1.IC Analog / Digital Full Layout 2.需求條件: 熟悉Laker,具有ESD 觀念佳 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才,共創A+聯詠
1.IC Analog / Digital Full Layout 2.需求條件: 熟悉Laker,具有ESD 觀念佳 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才,共創A+聯詠
1. 負責產品之佈局、DRC、LVS, 並產生供光罩製作之data base。 2. 具IC佈局相關工作經驗,須了解製程與ESD、Latch up。 3. 熟悉 Laker, Calibre.
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.
1.對類比IC Layout 有興趣者, 英文中等, 歡迎非本科系 2.無工作經驗可 3.相關科系.有英文相關證照者佳
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.
因應擴廠,擴大徵才 1.Sorting/AOI/Vcsel程式及人員機台掌控 2.有管理經驗者為佳 3.熟悉C語言
1.IC fully layout 2.類比 IC Layout 經驗者佳或具APR經驗者。 3.具Tape out 量產經驗,能獨立處理Whole Chip者優先考慮 4.熟悉layout tool或verification tool等工具軟體的使用 5.懂 Latch-up/ESD/Cross-section 者優先考慮
工作項目: 1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation. 工作地點:南部科學工業園區-台南園區 應徵條件: 1. 大學以上電機資訊相關科系畢 2. 熟悉 IC 後段設計流程, 具相關 APR 經驗者佳. 3. 對於開發及推廣 Physical Design Flow 有興趣者. 4. 熟悉相關 tools(Astro, Encounter, IC Compiler)者尤佳 5. 具程式設計(TCL,Perl,C/C++)能力者佳。
Job function: 1. Work with Digital Design team for Physical Design of SoC chips including top level floor planning, block partition, timing budgeting, power planning, block integration, whole chip timing closure, and tape out. 2. Responsible for physical design methodology research and development. 3. Cross site projects coordination and management. Requirement: 1. MS with 5+ years of experience in Physical Design. 2. Familiar with Unix/Linux environment and scripts. 3. Familiar with ASIC design flow. 4. Familiar with Physical Design EDA tools. 5. Good communication and team working skills. 6. Experience in handling large scale SoC chip implementation is a plus.
工作項目: 1. CPU & GPU Backend Implementation (APR) 2. CPU/GPU Backend Flow Development, Enhancement & Automation 3. Advanced CPU/GPU Technology Development: High-performance, Low Power, and PPA Optimization 應徵條件: 1. 碩士以上;電機、資工、電子相關科系畢業為主。 2. 熟悉 APR Tools (Innovus、ICC2、Fusion Compiler…),有Synthesis、STA/IR Analysis、Physical Verification等相關經驗者佳。 3. 具備程式設計能力,熟悉 TCL/Perl/C++/Python。 4. 有 High Performance CPU/GPU APR經驗尤佳。 5. 個性積極負責、勇於迎接新挑戰,對於 High-Performance CPU/GPU Technology 有興趣者。
1. 負責IC版圖的佈局佈線、優化和驗證。 2. 負責部分全定製版圖的設計和驗證。 3. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。
1. Analog IC layout 2. Chip integrate