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5/07 類比IC設計工程師(高雄)

  • 高雄市前鎮區
  • 2年以上
  • 碩士

1)Product definition and architectural development. 2)System level and transistor level design and validation using Cadence design tools. 3)Layout supervision and verification. 4)Prototype evaluation. 5)Test development. 6)Product characterization and quality assurance including burn-in, latch-up and ESD. 7)Failure analysis and yield enhancement. 8)Product release to production

待遇面議 員工70人
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0~5人應徵

4/26 Senior DFT Implementation Engineer_Kaohsiung (Foreigners are welcomed to apply)

  • 高雄市前鎮區
  • 5年以上
  • 碩士

Job Contents: - Communicate with customers to provide suitable test architecture planning for project scope - Working with the APR team to ensure to correct DFT implementation (SCAN/MBIST/Boundary Scan) and timing closure(STA) - Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check - Simulating and verifying the ATPG patterns - Support ATPG pattern debug on tester if need

待遇面議 員工100人
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0~5人應徵

呃拍謝，搜尋結果好像很少

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5/06 A-11 (台南)類比IC設計工程師 (車載整合)

  • 台南市永康區
  • 3年以上
  • 碩士

【產品範疇】 TV/NB - TV, NB, tablet and monitor display drivers 【工作內容】 Project management 1. Project specification definition 2. Whole chip planning and integration 3. Mixed mode circuit design and verification 4. Whole chip co-simulation 5. Co-working with PM/Layout/TE/AE/FAE/SA 【需求條件】 1. MS or PHD degree in EE 2. Good communication skills and simulation design knowledge 3. Familiar with OPUS, ADE.. etc. EDA tools 4. Familiar with HSPICE, XA, Finesim..etc. simulation tools 5. ESD and LU protection design concept

待遇面議 員工600人
0~5人應徵

5/03 類比IC設計工程師-Analog Design Engineer

  • 新竹市
  • 經歷不拘
  • 大學

Description of Talent Job Requirement職務說明 1. 5+ years experiences in ASIC/SOC mixed-signal circuitry design is a plus 2. Experienced on any multiple design of following analog IPs: IO, band-gap, DLL, PLL, POR, Comparator/Amplifier, ADC,DAC analog circuit design, modification, testing/,validation. 3. Familiar with IO　circuit design, Latch up/ESD protection mechanism , signal integrity quality control ,power , and IR drop 4. Familiar with Analog, memory IP, special circuitry library cell behavioral model 5. Solid discipline to perform flow of Analog design, layout plan and layout review, post-sim, modification for target and margin 6. Familiar with analog design flow and analog IP integration on SoC, power plan, performance ,cross talk is a plus 7. Experience with SoC failure mode on EMMI/ORBICH methodology and debug strategy 8. Familiar analogy IP behavior model and timing lib creation or modification for SoC integration is a plus 9. Good team work and new technology learner spitits 10. English communication capability is a must 11. Able to write design document , test report and failure analysis report structurally in English and Chinese

待遇面議 員工30人
6~10人應徵
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