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3/11 【Penang Branch】Analog IC Design Engineer

  • 馬來西亞
  • 2年以上
  • 大學

• Analog IC Design Engineer with specialization in CMOS Sensor, Analog/ Mixed Signal IC Design. • Design analog and mixed signals ICs in 0.11um, 0.18um and 0.25um technology for imaging sensor and capacitive touch sensor IC. • Develop new architectures and circuits for sensor ICs which consist of image sensor, amplifier, ADC, LDO, LED/ Laser driver, oscillator, active filter, bandgap, power on reset, IO, etc. • Perform IC definition, circuit design, simulations, post silicon verification and tests. • Perform full chip level integration, mixed-signal verifications & system level qualifications. • Conduct thorough design reviews. • Interface with various groups during the design cycle including system, digital and physical design teams.

待遇面議 上市上櫃 員工500人
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0~5人應徵

呃拍謝,搜尋結果好像很少

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4/25 Staff Analog IC Design Engineer

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待遇面議 外商公司 遠端工作
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- Responsible for architecture and design of power management IC (PMIC). Will perform hands-on circuit design, simulation, and verification of circuit blocks such as Buck converter, LDO, comparator, op-amps and other analog circuits. - Develop behavioral modeling of PMIC analog and digital circuits. Complete mixed signal simulations for verification of chip level and system level performance. Also responsible for evaluating, measuring, and debugging before production. 1.熟悉PMIC架構, 及類比電路的設計原理與電路特性 2.善用Scope, measurement instrument進行產品Debug 3.規劃晶片的驗證時程,並針對各種電路進行分析,確認電路特性符合規範

待遇面議 上市上櫃 員工190人
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4/26 類比IC設計工程師-Analog Design Engineer

  • 新竹市
  • 經歷不拘
  • 大學

Description of Talent Job Requirement職務說明 1. 5+ years experiences in ASIC/SOC mixed-signal circuitry design is a plus 2. Experienced on any multiple design of following analog IPs: IO, band-gap, DLL, PLL, POR, Comparator/Amplifier, ADC,DAC analog circuit design, modification, testing/,validation. 3. Familiar with IO circuit design, Latch up/ESD protection mechanism , signal integrity quality control ,power , and IR drop 4. Familiar with Analog, memory IP, special circuitry library cell behavioral model 5. Solid discipline to perform flow of Analog design, layout plan and layout review, post-sim, modification for target and margin 6. Familiar with analog design flow and analog IP integration on SoC, power plan, performance ,cross talk is a plus 7. Experience with SoC failure mode on EMMI/ORBICH methodology and debug strategy 8. Familiar analogy IP behavior model and timing lib creation or modification for SoC integration is a plus 9. Good team work and new technology learner spitits 10. English communication capability is a must 11. Able to write design document , test report and failure analysis report structurally in English and Chinese

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負責USB4相關產品專案開發。 1.Design of high-speed analog circuit 2.Post silicon debug 3.Monitor layout 4.Mentoring junior candidate 職務條件: 1.Must be able to communicate with team members in English. 2.Knowledge of layout floorplanning and support post silicon validation (for senior candidate). 3.Knowledge of design High speed (>10 Gbps) mixed signal protocol such as USB, PCIe, Ethernet (10G-KR) etc,. 4.Proven silicon record for experienced candidate.

6~10人應徵
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