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4/26 Jounior Physical Design Engineer (Malaysia)

  • 馬來西亞
  • 經歷不拘
  • 大學

1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.

待遇面議 員工500人
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0~5人應徵

4/26 Sr. Physical Design Engineer (Malaysia)

  • 馬來西亞
  • 3年以上
  • 大學

1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.

待遇面議 員工500人
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0~5人應徵

呃拍謝，搜尋結果好像很少

可以嘗試調整條件、或看看你專屬的推薦工作

推薦工作

4/26 SoC Physical Design Engineer (內湖)

  • 台北市內湖區
  • 1年以上
  • 大學

1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.

待遇面議 員工500人 距捷運劍南路站約500公尺
11~30人應徵

4/30 Sr. APE Engineer

  • 新竹縣竹北市
  • 5年以上
  • 大學

1. Provide IC package solution supporting pre-sales activity; timely respond package inquiries. 2. Collaborate with subcontractor's engineering team and IC designer to deliver robust package solutions. 3. Participate IC package substrate design, design review; initiate package specs and documentation. 4. Work with DE/PM, subcontractor for prototype build, package characterization and simulation.

待遇面議 員工500人
6~10人應徵

4/26 APR Physical Design / CAD工程師

  • 新竹縣竹北市
  • 2年以上
  • 大學

• Work on 22nm~6nm design implementation, methodology, and sign-off • Perform floorplan, power plan, place and route, timing closure, ECO, early IR signoff, and early physical verification • Manage schedule, resolve design and flow issues, drive methodologies and execution • Requirement： - Hands on whole chip APR physical design from netlist to DRC/LVS tapeout - Familiar with Cadence Innovus & Synopsys ICC/ICC2 experience is required

待遇面議 員工1100人
11~30人應徵
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