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7/19 數位ic設計工程師

  • 新竹縣竹北市
  • 3年以上
  • 大學

1. 高速介面設計經驗(USB, PCIe, MIPI, DDR, 等等) 2. SoC設計整合經驗與熟悉Tape-out流程 3. FPGA 設計驗證經驗 4. 熟悉AMBA架構、CPU架構 5. Low power經驗(UPF/CPF)

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6~10人應徵

7/19 IP/SoC 驗證經理/工程師

  • 新竹縣竹東鎮
  • 經歷不拘
  • 大學

TESDA 是一家快速成長的初創公司,正在尋找具有 5 年經驗的經理和 1~3 名數位設計驗證工程師。 作為 TESDA 的設計驗證工程師,您將能夠接觸和驗證來自世界級公司的複雜SoC 設計,除了具有競爭力的薪資還有現金及股票分紅。 如果您正在尋找可以為個人職業和財務成長,提供巨大增長機會的職位以及工作與生活平衡,那麼 TESDA 就是您的理想之選! 1. Mainly responsible for system-level design verification 2. Develop test plans, test platforms, test cases, reference models, coverage models, and regression suites 3. RTL simulation/function verification/fault debugging 4. Drive and achieve coverage closure 5. Familiar with ARM or RISC-V & AMBA bus protocol is a plus. 6 Familiar with SVA/UVM test platform framework is a plus

待遇面議 員工20人
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6~10人應徵

7/19 產品硬體測試研發工程師 Hardware Engineer

  • 台北市南港區
  • 5年以上
  • 大學

Job summary: Responsible for product verification and development of Qualcomm platform, integrating MCU/video/image/acoustic/high speed signals/power conversion design. 負責高通平台的產品驗證開發,整合MCU/video/image/acoustic/high speed signals/電源轉換設計。 Duties/ Responsibilities: - Design production testing accessories and platforms. - Circuit drawing and debugging. - Cooperate with software developers to set up test and verification environment. - Test platform planning and proposal. - 設計製作相關測試配件與平台 - 電路繪製與除錯 - 與軟體開發協助合作測試驗證環境架設 - 測試平台規劃與提案 Requirements: - To possess more than 5 years of SOC/video/image product development experience. - Familiar with multi-core high-speed CPU platform and related practical experience in high-speed signal processing, sensors/power supply design, EMI/EMC/E Qualification Test and other protection designs. - Possess professional knowledge of ORCAD/mentor, Allegro, EMI/EMC/ESD protection. - Supplier technology evaluation, production efficiency and quality optimization. - Willingness to cooperate with customer time zone telephone conferences and technical support for overseas business trips. - 須具備五年以上 SOC/video/image產品開發經驗。 - 熟悉多核高速CPU平台及相關高速訊號處理,sensors/電源設計,EMI/EMC/E-Qualification Test等防護等設計之實務經驗。 - 具備ORCAD/mentor, Allegro, EMI/EMC/ESD防護專業知識。 - 供應商技術評估,生產效率與品質優化。 - 能配合客戶時區電話會議與國外出差技術支援。

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6~10人應徵

7/19 【新鮮人專區】2024研發替代役/預聘-數位設計工程師

  • 新竹市
  • 經歷不拘
  • 碩士

此專區為符合2024年研發替代役及預聘者投遞,如非研替/預聘身分者,歡迎投遞創未來其他職缺! ##職務類別 1. 數位設計工程師 2. 數位前端整合工程師 3. 數位自動化測試工程師 4. 韌體工程師 ##工作內容 1. 應用於雷達、數位感測、衛星通訊之訊號處理數位IP設計。 2. 數位IP架構設計與實作。 3. FPGA數位系統開發與整合合成優化。 4. 微波、類比電路控制、校準設計韌體實作 。 ##技能需求 1. 具數位訊號處理經驗。 2. 具備數位電路設計經驗。 3. 熟悉Verilog/VHDL、TCL等。 ##應徵資格 1. 2024年畢業之應屆碩/博畢業生。 2. 研究所以上電子/電機/電信/通訊相關科系畢業。 3. 欲應徵者請檢附成績單、論文摘要。

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6~10人應徵

7/19 Senior DFT Implementation Engineer_Kaohsiung (Foreigners are welcomed to apply)

  • 高雄市前鎮區
  • 5年以上
  • 碩士

Job Contents: - Communicate with customers to provide suitable test architecture planning for project scope - Working with the APR team to ensure to correct DFT implementation (SCAN/MBIST/Boundary Scan) and timing closure(STA) - Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check - Simulating and verifying the ATPG patterns - Support ATPG pattern debug on tester if need

待遇面議 員工100人
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0~5人應徵

7/19 APR工程師/資深工程師

  • 新竹縣竹北市
  • 3年以上
  • 大學

1. 負責後段APR flow   Familiar Netlist-to-GDS Design flow. Including,Floorplan/Power Plan/IR drop analysis、Placement/CTS/Route、Timing Analysis . 2. Physical Verification. Including, -DRC/LVS to tapeout. 3. 需參與團隊, 合作完成專案  

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0~5人應徵

7/19 SoC數位IC設計工程師

  • 新竹縣竹北市
  • 3年以上
  • 大學

1. ASIC開發數位電路設計,協助客戶制定規格並提供技術協助 2. SoC硬體整合及驗證環境之研發與客戶服務 3.具專案管理能力

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6~10人應徵

7/19 【大型 IC 設計公司】CPU IC Designer 高效能處理器設計工程師_207HC

  • 台北市松山區
  • 9年以上
  • 大學

高效能處理器設計工程師  職務內容: 1. ARM CPU subsystem platform design & integration 2. CPU post-silicon issue resolving  職務要求: 1. RTL design for specific CPU subsystem features 2. RTL sign-off including Spyglass-Lint, Spyglass-DFT, CCD, CCD check, etc. 3. RTL simulation issue resolving 4. Provide design timing constraint (sdc) and power domain information 5. CPU post-silicon issue resolving

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0~5人應徵

7/19 設計驗證工程師

  • 新竹縣竹北市
  • 經歷不拘
  • 學歷不拘

1.針對數位電路IP Spec撰寫testcase 與相容性測試 2.有SOC與FPGA前端驗證經驗 3.熟悉數位IC設計流程和相關EDA工具 4.有大型複雜電路或serdes CTRL驗證經驗者尤佳

待遇面議 員工7人 遠端工作
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11~30人應徵

7/19 Design Verification Engineer, PCIe

  • 台北市內湖區
  • 2年以上
  • 大學

NVIDIA is seeking an elite Verification Engineer to verify the design and implementation of the next generation of PCI Express controllers for the world’s leading GPUs and SOCs. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We're united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science. The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA’s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as “the AI computing company.” What you’ll be doing: - Verification of the ASIC design, architecture, and micro-architecture of PCIE controllers for multiple product generations for GPUs, SOCs & DPUsat IP/sub-system levels using standard verification methodologies such as UVM and Specman/e. - Develop UVM or Specman/e based testbench components reusable across verification methodologies and integrate those across verification environments. - Build or improve reusable testbench components including constraints, stimulus, monitors, checkers and scoreboards following coverage based verification methodology. - Understand complex testbench and its verification scope with respect to the design specification and implementation, define new verification scope as per design or verification methodology requirements, develop test plans, tests, and the verification infrastructure and verify the correctness of the design. - Collaborate with multiple verification teams, architects, designers, and pre and post silicon verification teams to accomplish your tasks. What we need to see:  - B.Tech./ M.Tech. with 2+ years of relevant experience - Experience in verification at Unit/Sub-system/SOC level using Verilog and SystemVerilog - Background with verification of IP or interconnect protocols (e.g. PCI Express, USB, SATA) - Experience in developing and working in functional coverage based constrained random verification environments - Experience in DV methodologies like UVM/VMM and exposure to industry standard verification tools for simulation and debug Ways to stand out from the crowd:  - Knowledge of PCIE protocol - Gen3 and above - Proficiency in Testbench development using SystemVerilog - Perl, Python or similar scripting and SW programming language experience - Good debugging and analytical skills - Good interpersonal skills & dream to work as a great teammate With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We have some of the most brilliant and talented people in the world working for us. If you are creative, autonomous and love a challenge, we want to hear from you. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.

待遇面議 外商公司 員工18975人 遠端工作
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6~10人應徵

7/19 [New College Graduate新鮮人專區] DFT Engineer

  • 台北市內湖區
  • 經歷不拘
  • 大學

Senior DFT Engineer Location: Taiwan, Taipei Taiwan, Hsinchu NVIDIA is seeking phenomenal engineers to improve our DFT methodology, so we can validate the world’s largest design efficiently. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of extraordinary people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. We are now looking for a Senior DFT Engineer in our Taiwan, Taipei/Hsinchu Office! What you’ll be doing: -Implement testing architecture of VLSI -Generating test patterns and chip bringup -Develop testing methodology for VLSI -Develop design flow for testing What we need to see: -Master degree of Electrical Engineering/Computer Engineering/Computer Science -Good understanding of Design for Testing including Scan/ATPG/BIST/JTAG -Familiar with Verilog -Experiences with RTL and Simulation. -Understanding of Timing is plus -Skills of C/C++/Perl/Tck is a plus Ways to stand out from the crowd: -English communication is required. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most brilliant and talented people on the planet working for us. If you're creative and autonomous, we want to hear from you!

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11~30人應徵

7/19 【力碁業務處】RF工程師,硬體工程師,RF IC設計工程師,數位IC工程師(台中)

  • 台中市西屯區
  • 1年以上
  • 大學

針對智慧電錶的應用(太陽光電/儲能/需量反應/售電) 1. 制定電信或網路通訊產品(如:Router、VPN、Ethernet、MPLS、SDH、ATM、FR、VOIP、DACS)之系統規格。 2. 開發、評估電信或網路通訊相關之產品。 3. 進行市場趨勢研究,並開發電信或網路通訊之新技術。 4. 分析比較同業的產品,以提升、改善自身產品之競爭力。 5. 擔任團隊領導與跨部門溝通協調之角色,並負責研發專案相關之行政管理工作。 6. 負責生產技術及生產設備之開發或引進。 7. 掌控與督導產品開發之進度。 8. 提供內部同仁或外部客戶技術指導及支援。

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6~10人應徵

7/19 類比IC設計工程師(高雄)

  • 高雄市前鎮區
  • 2年以上
  • 碩士

1)Product definition and architectural development. 2)System level and transistor level design and validation using Cadence design tools. 3)Layout supervision and verification. 4)Prototype evaluation. 5)Test development. 6)Product characterization and quality assurance including burn-in, latch-up and ESD. 7)Failure analysis and yield enhancement. 8)Product release to production

待遇面議 員工70人
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0~5人應徵

7/19 IC Testing & Validation Engineer-Optical Module-IC測試驗證工程師

  • 新竹縣竹北市
  • 2年以上
  • 專科

Artilux is now seeking a passionate Testing & Validation Engineer to join our team. We are committed to developing innovative optical module products. The candidate will work closely with cross-functional teams from the design phase through product launch to ensure our product quality and performance are of the highest standards and meet customer expectations. Key responsibilities for this role include: 1. Make plans and outline details to test the optical module and IC. 2. Establish the test environment, including test platforms, test scripts, and simulation models. 3. Perform the test, collect data, and analyze test results. 4. Collaborate closely with RD, EE, FW, SW, and optical teams throughout the test development process to ensure the design meets specifications, identifying and correcting design errors. 5. Generate test reports, and summarize test results to propose product improvements. *Actual compensation will be determined based on qualifications, educational background, relevant work experience, professional certifications, special skills, and language proficiency.

待遇面議 員工100人
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11~30人應徵

7/19 數位 IC 設計工程師 I

  • 新竹市
  • 經歷不拘
  • 碩士

1. 數位電路設計、模擬與驗證 2. AMBA(AHB/APB)與IP整合 3.微控制器、微處理器架構設計 4.Audio/Speech相關演算法開發與設計 5.協助開發與驗證FPGA電路 6.RTL Synthesis , Design Timing Constraint 7.POR、BOR、LVR、IO PAD、PWM、Level-shifter、SRAM、ADPLL設計(SPICE simulation)

待遇面議 上市上櫃
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11~30人應徵

7/19 【國際知名大型 IC 設計公司】RISC-V Senior CPU IC Designer_207HC

  • 台北市松山區
  • 9年以上
  • 大學

Job Description • CPU architecture design (RISC-V ) • In-order/out-of-order micro-architecture analysis and design • CPU modeling and Linux/benchmark analysis Requirement • Experienced in CPU architecture. Familiar with RISC-V ISA. • Experienced in L1/L2 cache subsystem and AXI/CHI design. • Experienced in Gem5 modeling, and performance analysis

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0~5人應徵

7/19 Senior Research Scientist, Design Automation (EDA)(AI)

  • 台北市內湖區
  • 經歷不拘
  • 博士

NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It’s a unique legacy of innovation that’s fueled by great technology—and amazing people. Today, we’re tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what’s never been done before takes vision, innovation, and the world’s best talent. As an NVIDIAN, you’ll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world. What you will be doing: NVIDIA Design Automation research group is seeking research scientists in the areas of AI for chip design and GPU accelerated EDA. Deep learning and GPU advancement are changing the landscape of chip design. In this position, you will conduct original research across broad technical areas including EDA algorithms and software, machine learning, and VLSI chip design methodology. Specific areas of research interest include but are not limited to applications of supervised learning, unsupervised learning, reinforcement learning and GPU acceleration to EDA algorithms. - Apply deep learning and GPU acceleration to EDA software and ASIC and VLSI design tool flows. - Research and develop creative and innovative EDA software and algorithms. - Collaborate with circuits, VLSI, and architecture team members in research and product teams. - Publish and present your original research, speak at conferences and events - Collaborate with external researchers and a diverse set of internal product teams. What we need to see: - PhD in Computer Science, Computer Engineering, Electrical Engineering, or related field. - Strong publication record in leading EDA or ML conferences on DL for EDA or GPU accelerated EDA. - Strong knowledge in one or more EDA/VLSI fields and deep learning - Excellent programming skills in two of Python/PyTorch/C++/CUDA. - Ability to work independently. Ways to stand out from the crowd: - Publishing record on top AI conferences - High impact open-source tools developer - Strong communication skills. Creative and dynamic presenter.

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6~10人應徵
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