1. 熟悉Verilog與FPGA環境與操作，能開發prototype。 2. 具備USB/PD/DP/HDMI等protocol設計相關。 3. 有高速介面設計經驗佳。 4. 具備Synthesis, STA, Formal verification, CDC等經驗。 5. 有演算法開發基礎, 在Matlab環境下做算法開發。
1. IC設計流程自動化開發與維護 2. EDA軟體/IP安裝與管理 3. Linux系統維護和操作
Job Contents: - Communicate with customers to provide suitable test architecture planning for project scope - Working with the APR team to ensure to correct DFT implementation (SCAN/MBIST/Boundary Scan) and timing closure(STA) - Provide LEC and SDC scripts for Formal Verification and Timing Constraint Check - Simulating and verifying the ATPG patterns - Support ATPG pattern debug on tester if need
1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
Job Contents · Perform Netlist-to-GDS design flow, including floor planning, placement, timing optimization, clock tree synthesis and routing. · Support STA timing analysis and fixing. · Perform physical verification, including DRC, LVS, IR drop and DFM analysis.
1. Front-end design flow development 2. Logic Synthesis, STA, LEC, ECO flow creation and consultant
本職缺主要工作內容為I/O電路設計, 從較低速一般應用的GPIO, 到較高速特定介面應用的I/O (ex: SD, eMMC, ONFi, DDR, …etc.) 均有機會接觸與開發。針對計畫需求亦會開發客製化I/O以因應各式特殊需求。因I/O與ESD/Latch-up息息相關，亦會學習設計並review ASIC ESD floorplan。此外，開發的DDR I/O 會被公司內的DDR-PHY IP使用，未來若有興趣，可選擇繼續往DDR-PHY高速介面發展，抑或協助設計DDR-PHY中所需要的Analog block。
· Proficiency in Python* and TCL and experience across multiple scripting languages. · Experience with LSF or equivalent distributed computing environment · Experience with CAD flow, script development and maintenance · Experience with automation and data logging of tool usages
我們正在尋找一位熱情、有經驗的EDA應用工程師，加入我們充滿創新和技術挑戰的團隊。這位工程師將與台灣地區的客戶及合作夥伴緊密合作，提供最新的電子設計自動化工具和技術支援，以實現客戶的設計最佳化及效率提升。 職責： 與客戶端的工程師密切合作，了解其設計需求，提供EDA工具相關的技術支援。 協助客戶優化和自動化設計流程，以提高生產力和效率。 在EDA工具中執行模擬和分析，確保客戶設計的性能、功耗和可靠性符合要求。 解決客戶在設計過程中遇到的技術挑戰，提供解決方案以滿足其產品開發目標。 資格要求： 學士或以上學歷，專業領域包括電子工程、計算機工程或相關領域。 具備良好的問題解決和溝通能力，能夠有效協作並在客戶團隊中發揮領導力。 對IC設計、半導體及EDA產業有濃厚興趣，並追求不斷學習和專業成長。 優先條件： 具有DV (Design Verification)驗證經驗。 具有UVM (Universal Verification Methodology)經驗。 具有相關EDA工具（如Cadence、Synopsys、Mentor Graphics等）的使用經驗。 熟悉硬體描述語言（SystemVerilog、Verilog、VHDL）和模擬工具。
General OSC/PLL/DLL/SSCG/CDR design & production experience 1) LC-tank VCO design & production experience 2) CDR design & production experience
1. Know how to communicate with testing house about the testing program and product engineering. 2. Work closely with the engineering design team to solve yield and quality problems. 3. Analyze product defect reasons.
1. Study / research / develop DFT design flow 2. Maintain inhouse DFT utilities.
1. FPGA IP/RTL開發、模擬與驗證 2. FPGA相關演算法開發 3. 特殊航太產品FPGA相關應用 4. 使用Verilog、VHDL開發語言 5. FPGA 產品設計驗證流程 6. 軟/硬體系統設計整合 7. 公司指派任務
【工作內容】 1. 數位電路邏輯控制程式設計 2. 基本通訊界面控制 (UART/I2C/SPGIO/SPI) 3. CPLD規格評估 4. CPLD規格書規劃、撰寫、維護 5. Verilog/VHDL模擬除錯設計 6. CPLD測試、除錯、驗證及最佳化 7. 維護現有CPLD專案 【其他條件&加分項目】 1. 熟悉 Verilog, 2. 若具有 Altera Quartus II, Lattice Diamond , Modelsim能力佳 3. 具有開創性及解決問題的能力 4. 客戶導向及良好溝通技巧 5. 具備推動團隊完成任務的能力 6. 流程管理能力
1. Responsible for the main technical contact window and consultant of chip implementation from RTL-in/netlist-in to tape out for ASIC customers 2. Responsible for ASIC project management and coordination among internal supporting groups 3. Responsible for DFT implementation, including MBIST, Scan insertion, IO level testing, JTAG and ATPG generation 4. Responsible for ASIC constraint validation, including floorplan, timing, clock, package, power, and so on.
1. RTL design & simulation 2. Cell base design flow 3. Digital verification 4. Design documentation 孰悉以下工具: Verilog coding, 與 Cell base design flow 具有以下相關經驗尤佳: 1. Memory controller 相關經驗 2. low power design flow 相關經驗 3. MCU開發相關經驗 4.FPGA 開發與 SOC整合和驗證