4/26 【此職缺僅供有2024年研替身份之未役求職者投遞】類比IP設計工程師
- 敦泰電子股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 經歷不拘
- 碩士
SRAM, ROM and OTP interface電路設計
4/26 類比射頻IC設計工程師
- 環宇全球科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 5年以上
- 碩士
1.Experienced in CMOS VCO / DCO / LO generator and distribution / Frequency divider block design and trade-offs. 2.Experienced in CMOS frequency Synthesizer/Fractional-N PLL for low jitter and low power design. 3.Experienced in passive component design using EM tools (EMX/Sonnet/HFSS/…) 4.Experienced in RF/analog circuit simulation tools (SpectreRF/ADS…)
4/26 【派駐聯發科/新竹U】 CAD engineer – Static timing analysis/AL
- 就業情報資訊股份有限公司
- 人力仲介代徵
- 新竹市
- 經歷不拘
- 大學
1. Spice simulation for advanced process effect 2. simulation flow程式維護修改 3. STA execution for timing flow regression. 4. 提供3個月Internal training，並有on-job training with mentor 5. 工作細節請參照下方工作內容參考URL # https://kknews.cc/zh-tw/news/5vxbn8.html (Static Timing analysis中文簡介) # https://www.youtube.com/watch?v=fFUyEU77XuA # https://www.youtube.com/watch?v=xY63pG1gYuM
4/26 Senior OLED-Driver Analog IC Designer (Technical Manager)
- 台灣利優資訊科技有限公司
- 人力派遣服務
- 新竹市
- 8年以上
- 碩士
JD: - Lead the specification formulation of the simulation part of the capacitive touch chip - Responsible for chip architecture, IP selection, and key module circuit design, including ADC/DAC/PLL/op-amp/AFE, etc. - Lead the technical feasibility analysis of the simulation part of the capacitive touch chip, and determine the overall architecture - Formulate Project planning and completion on time with high-quality _ According to specifications and technical specifications, design and implement specific circuit architecture. Led the analog design team to complete analog circuit design, simulation, and verification, and be responsible for writing-related design reports. - Plan the layout, and guide the layout engineer to complete the simulation layout that meets the circuit performance requirements and post-imitation. - Assist the test engineer in formulating the CP/FT/laboratory test plan related to the simulation, assist in the design of the test board, and assist the test engineer in solving the problem. Problems in the debugging process; 8. Responsible for the test and verification of the chip simulation part, leading the Debug work of the chip simulation part - Assist AE and FAE to provide technical support and solutions for customer feedback and needs; 10. Responsible for the development of related product simulation design and control of the entire process. Other Requirements: - Master's degree or above, major in microelectronics, electronic engineering, more than 8 years of working experience in analog IC design - Experience in TouchIC design, operational amplifier circuit, charge measurement circuit, ADC successful mass production is preferred - Understand semiconductor technology & its process, familiar with CMOS/BiCMOS/BCD process and high voltage device principle - Familiar with ESD principles and design methods, have a deep understanding of I/O related ESD, Latch-up design, and be able to guide the specific layout design of this part -Good command of English, strong communication skills, and a good sense of teamwork.
4/26 【派駐聯發科/新竹U】CAD engineer – APR/IR drop analysis/AL
- 就業情報資訊股份有限公司
- 人力仲介代徵
- 新竹市
- 經歷不拘
- 大學
1. IRdrop execution for IR sign-off flow regression. 2. Utility maintenance of APR placement rule 3. 提供3個月Internal training，並有on-job training with mentor 4. 工作細節請參照下方工作內容參考URL # https://www.youtube.com/watch?v=LMDiRO9QNtE ( What is Physical design 英文影片) # https://www.youtube.com/watch?v=9QvK6083no8 (IR drop analysis flow英文影片)
4/26 類比IC設計工程師 (新竹/內湖)
- 鴻軒科技股份有限公司
- 電腦軟體服務業
- 新竹市
- 3年以上
- 碩士
1. 類比IP相關功能的設計與實現 ADC, DAC, OSC, PLL, high speed interface...etc. 2. 類比IP設計方法和品質改進 3. 類比IP仿真與分析 4. 與第三方類比 IP 供應商合作 5. 與數位電路作co-sim
4/26 Layout_(Sr.) Engineer/Technical (Assistant) Manager
- 乾瞻科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 3年以上
- 大學
analog and digital circuit layout繪製
4/26 【實習人才培育計畫】
- DIGWISE_崛智科技股份有限公司
- 電腦軟體服務業
- 新竹縣竹北市
- 經歷不拘
- 專科
在我們的實習過程中，您將有機會在專案中擔任以下角色： 1. 數位IC設計EDA工程師 (CAD Engineer) 2. 數位IC電路設計工程師 (Standard Cell Design Engineer) 3. 數位IC佈局工程師 (Standard Cell Layout Engineer) 4. 數位IC實體設計工程師(Physical design Engineer) ※ 應徵者請附上完整履歷及自傳。
4/26 類比IC設計工程師
- 佑華微電子股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 大學
MCU相關類比電路設計：RCOSC , Xtal , Bandgap , LDO , OPAMP , DAC , ADC , POR , LVD 等.
4/26 類比/資深類比IC設計工程師(台北/新竹)
- 新竹縣竹北市
- 3年以上
- 碩士
1. 類比數位轉換器，數位類比轉換器(ADC/DAC), 2. Mixed-Signal & Analog Circuits (Switched-Capacitor Circuit, Bandgap, etc), 3. Analog-Front-End (AFE), Sensors, and Power Related IC (LDO, PoR, DC-DC, Bulk, Boost Converters). 4. 鎖相迴路設計、全數位式鎖相迴路設計、SerDes 5. Clocking related:PLL, DLL, CDR, TDC
4/26 類比及高速線路IC設計工程師
- 翊傑科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 大學
Description of Talent Job Requirement職務說明 1.(Manger or Director)15+ years mixed signal ASIC/SOC design circuitry design and team manage experience (Sr. Engineer or Engineer) 3+ years experiences in ASIC/SOC mixed-signal circuitry design is a plus 2. Experienced on any multiple design of following analog IPs: IO, band-gap, DLL, PLL, POR, Comparator/Amplifier, ADC,DAC ,Sensor array, MRAM Macro, ReRAM macro, design, modification, testing/,validation. 3. Familiar with IO circuit design, Latch up/ESD protection mechanism , signal integrity quality control ,power , and IR drop 4. Familiar with Analog, memory IP, special circuitry library cell behavioral model 5. Solid discipline to perform flow of Analog design, layout plan and layout review, post-sim, modification for target and margin 6. Familiar with analog design flow and analog IP integration on SoC, power plan, performance ,cross talk is a plus 7. Experience with SoC failure mode on EMMI/ORBICH methodology and debug strategy 8. Familiar analogy IP behavior model and timing lib creation or modification for SoC integration is a plus 9. (Manager/Sr. Engineer) Able to communicate with customers and transfer technical specifications to IC design specification for feasibility study , and create project database to perform multi-people work on same project data for IC design. 10. Good team work and new technology learner spirits 11. English communication capability is a must 12. Able to write design document , test report and failure analysis report structurally in English and Chinese
4/26 SI/PI Simulation_(Sr.) Engineer/Technical (Assistant) Manager
- 乾瞻科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 2年以上
- 碩士
1.Whole system signal and power integrity modeling and simulation including IP (DDR and other interface IP such as MIPI, PCIE, etc.), package and PCB. 2.Package and PCB model extraction for SI/PI simulation. 3.Co-work with IP designers to simulate and solve IP and system level SI/PI issues.
4/26 DDR PHY_(Sr.) Design Engineer/Technical (Assistant) Manager
- 乾瞻科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 經歷不拘
- 碩士
* 電子/電機相關科系畢業 * 具DDR PHY 相關設計經驗佳 * 對DRAM系統，JEDEC spec有相對的理解 * Familiar with Spice simulation
4/26 ESD/TVS 研發工程師
- 新竹市
- 2年以上
- 碩士
1. ESD保護元件設計 2. EOS/Surge保護元件設計 3. 積體電路系統ESD防護設計 4. 協助RD處理製程問題、與製程廠聯繫、以及Tapeout，MT Form等相關事宜
4/26 Senior Standard Cell Design Engineer (台北/新竹/高雄)
- 新竹縣竹北市
- 3年以上
- 碩士
1. Be familiar with std-cell library design, Experience with high-speed/low-power. 2. Be the key role to speed up your colleagues' daily work, including circuit design, PPA analysis, cell characterization and QA flow. 3. Feature of std-library circuit optimization (STD analysis). 4. Project management-STDL cell library circuit design. 5. Experience with FinFET process, 16/12; 7/5nm
4/26 類比IC設計工程師-Analog Design Engineer
- 翊傑科技股份有限公司
- IC設計相關業
- 新竹市
- 經歷不拘
- 大學
Description of Talent Job Requirement職務說明 1. 5+ years experiences in ASIC/SOC mixed-signal circuitry design is a plus 2. Experienced on any multiple design of following analog IPs: IO, band-gap, DLL, PLL, POR, Comparator/Amplifier, ADC,DAC analog circuit design, modification, testing/,validation. 3. Familiar with IO circuit design, Latch up/ESD protection mechanism , signal integrity quality control ,power , and IR drop 4. Familiar with Analog, memory IP, special circuitry library cell behavioral model 5. Solid discipline to perform flow of Analog design, layout plan and layout review, post-sim, modification for target and margin 6. Familiar with analog design flow and analog IP integration on SoC, power plan, performance ,cross talk is a plus 7. Experience with SoC failure mode on EMMI/ORBICH methodology and debug strategy 8. Familiar analogy IP behavior model and timing lib creation or modification for SoC integration is a plus 9. Good team work and new technology learner spitits 10. English communication capability is a must 11. Able to write design document , test report and failure analysis report structurally in English and Chinese
4/26 High-Speed SerDes_(Sr.) Analog Design Engineer/Technical (Assistant) Manager
- 乾瞻科技股份有限公司
- IC設計相關業
- 新竹縣竹北市
- 2年以上
- 碩士
* Familiar with High-speed SerDes (高速介面) PHY design such as PCIE, USB3, SATA, MIPI, MPHY, HDMI, etc. * Circuit design experience in any of the following aresa: PLL, SCPLL, Transmitter, Receiver and CDR.