1.mixed mode circuit design 2.DC-DC and LDO circuit design 3.PLL & Serdes circuit design 4.ESD, Latch up & I/O circuit design and debug 職務條件 1.熟悉以下領域：LDO/DC-DC/PLL Serdes/ESD & LU (至少一項) 2.具思考分析、獨立解決問題之能力、類比電路設計經驗者尤佳
1.負責Substrate 及 Lead frame 發包事宜 2.負責跟催及追蹤FAI Substrate 及 Lead frame 交期 3.負責 Bumping 交期與跟催 4.負責安排 FAI SMT 作業時程 5.主管交辦事項
1)Product definition and architectural development. 2)System level and transistor level design and validation using Cadence design tools. 3)Layout supervision and verification. 4)Prototype evaluation. 5)Test development. 6)Product characterization and quality assurance including burn-in, latch-up and ESD. 7)Failure analysis and yield enhancement. 8)Product release to production
1.具類比IC設計經驗 2.具ADC、DAC、PLL、High Speed Serial Link 等相關類比IC設計經驗者佳 3.諳低雜訊設計，具晶片整合經驗者佳 4.溝通表達能力佳，喜好腦力激盪，具團隊合作態度者
協助AC/DC研發團隊，開發相關高瓦特數產品IC。 專長: 1.AC/DC產品經驗，熟悉Flyback、QR、LLC架構或同步整流。 2.DC/DC產品經驗，熟悉相關電路設計。
類比IP/IC開發設計 專長: 1.熟悉ADC/DAC/OPAMP/Bandgap/OSC/PLL 2.具混合訊號電路設計/分析能力
呃拍謝，搜尋結果好像很少
可以嘗試調整條件、或看看你專屬的推薦工作
負責USB4相關產品專案開發。 1.Design of high-speed analog circuit 2.Post silicon debug 3.Monitor layout 4.Mentoring junior candidate 職務條件： 1.Must be able to communicate with team members in English. 2.Knowledge of layout floorplanning and support post silicon validation (for senior candidate). 3.Knowledge of design High speed (>10 Gbps) mixed signal protocol such as USB, PCIe, Ethernet (10G-KR) etc,. 4.Proven silicon record for experienced candidate.
1. Buck/Buck-Boost converter產品開發 2. Analog power IC design 3. Layout supervision and check 4. 量測且協助產品問題排除
SerDes PHY Circuit Design: 1. SerDes RX design, include CTLE, PGA, DFE… 2. SerDes TX design, clock buffer distribution, TX driver 3. be familiar with SerDes system operation.
We are looking for a senior engineer to be part of the mixed-signal design team building next generation NVLINK. This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL. You will have hands on experience taking innovative integrated circuit designs at data rates of 50Gbps and higher from concept through silicon characterization. What you will be dong: - Define circuit requirements and complete design from schematic, layout, and verification to characterization. - Conduct schematic design of deep-submicron CMOS technologies using Spectre, Hspice or like. - Take responsibility for the architecture, transistor design and verification using industry standard EDA tools such as Cadence virtuoso. - Optimize circuit to meet the specifications for system performance. - Work with layout engineers by providing detailed floorplan and guidance for matching and high-speed routings. - Provide support for post-silicon bring-up and debugging. What we need to see: - Master of Science or foreign equivalent degree in Electrical Engineering, Computer Engineering or related field with strong analog design background. - Minimum 2 years analog design experience in industry - CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET) - Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA) - Experience in crafting test bench environments for component and top level circuit verification - Behavioral modeling of analog and digital circuits - Strong debugging and analytical skills - Analog simulation for noise analysis, loop stability analysis, ac/dc/tran analysis, monte-carlo, etc. - Strong communication skills and ability & desire to work as a great teammate are huge plus. - All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, citizenship, disability or protected veteran status.
The candidate will work on high-speed and high performance Analog SerDes development in advanced technology nodes, 5nm, 3nm and beyond. Participate in SerDes Architecture Development with DSP, Analog and Digital design teams. Provide the instructions to the layout engineers. Working with the AE for the IP characterization and validation plan. Supporting IP Lab characterization and debugging. Product and customer supporting.