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3/11 【Penang Branch】Analog IC Design Engineer

  • 馬來西亞
  • 2年以上
  • 大學

• Analog IC Design Engineer with specialization in CMOS Sensor, Analog/ Mixed Signal IC Design. • Design analog and mixed signals ICs in 0.11um, 0.18um and 0.25um technology for imaging sensor and capacitive touch sensor IC. • Develop new architectures and circuits for sensor ICs which consist of image sensor, amplifier, ADC, LDO, LED/ Laser driver, oscillator, active filter, bandgap, power on reset, IO, etc. • Perform IC definition, circuit design, simulations, post silicon verification and tests. • Perform full chip level integration, mixed-signal verifications & system level qualifications. • Conduct thorough design reviews. • Interface with various groups during the design cycle including system, digital and physical design teams.

待遇面議 上市上櫃 員工500人
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0~5人應徵

呃拍謝,搜尋結果好像很少

可以嘗試調整條件、或看看你專屬的推薦工作

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3/28 類比IC設計工程師

  • 新竹縣竹北市
  • 5年以上
  • 碩士

Imagine being part of a team that is fundamentally changing the way people communicate, the way they collaborate, the way they watch TV and explore the universe through the internet. Utilizing our uniquely differentiated technology, we have created an Intelligent Transport Network with more speed, capacity and scalability than ever before. Imagine a world with unlimited bandwidth. The network of tomorrow will allow for content and creativity limited only by the imaginations of its users. If this is something that interests you, that excites you, come take a look at a team not bound by large company obstacles and bureaucracy, where an idea today can be set in motion tomorrow. Come take a look at Infinera! Engaging in the high-speed analog circuit design, you have the chance to create the technical differentiation for Infinera to hold the market leadership. We together will revolutionize the era of efficient high speed transmission by building the cutting-edge circuitry. Essential Functions and Key Responsibilities: • Design, implement, and simulate the functionality and performance of various high speed analog circuits, including the ADCs and DACs; • Create the layout floor plans to optimize the overall performance; Supervise the layout activities and give concise guidelines to layout engineers, need to be hands on in drawing layout if necessary; • Exploring the trade-offs of the different topologies and propose the best solution to achieve or exceed the requirements in terms of power/area/linearity/bandwidth, etc. • Develop the analog testing plans and work with the PE/TE teams to characterize the functionality and performance of the products to ensure the quality; • Need to support and comply with the team’s design methodologies and release flows. Mandatory Knowledge/Skills/Abilities: • Must be extremely familiar with essential CAD tools, such as Cadence Virtuoso, Spectre, Incisive, Calibre, EMX, and Totem EM/IR, etc. • Must have a proven tracking record of designing complex analog / mixed signal IPs or chips in deep submicron CMOS technologies. • Must have experiences in bringing high performance analog IPs including but not limited to high-speed ADC, high-speed DAC, and high-frequency low-jitter PLL to production. • Must have a decent understanding in CMOS analog / mixed signal design methodologies and circuit analysis; • Must have a good understanding of device physics and the impacts of layout effects; • Able to perform the behavioral modeling the blocks and circuits with Verilog-A or Verilog-AMS; • Collaborative with other local or remote team members in a fast-paced professional environment. Preferred Knowledge/Skill/Abilities: • Fluent in verbal and written communications; • Independently resolves issues and conquer design challenges; • Self-motivated and detail-oriented; • Has the knowledge of (optical) communication theories and Matlab coding. Education and Experience Requirements: • Principal Design Engineer: M.S. in E.E. with 12+ years’ experience, or Ph.D. in E.E. with 8+ years’ experience Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.

0~5人應徵

2/19 類比IC設計工程師

  • 新竹縣竹北市
  • 3年以上
  • 碩士

1. 電源管理 或 混訊類比IC設計(Bandgap, OPAMP, LDO, DC/DC, Charge Pumping)等。 2. 了解IC佈局並與Layout engineer co-work。 3. 與應用工程師討論系統應用並設計相關驗證方法。 4. 擅長工具: Hspice, Candence Virtuoso,Composer及Layout相關software等。

11~30人應徵

3/22 A-08 類比IC設計工程師(觸控類比IP)

  • 新竹縣竹北市
  • 經歷不拘
  • 碩士

【產品範疇】 1.Touch panel controller 2.TDDI 【工作內容】 1.Analog front-end design 2.ADC design 3.Switched-capacitor circuit design 4.負責layout floorplan規劃,與layout工程師合作完成相關驗證 【需求條件】 1.Device physics knowledge applied to analog IC design 2.Familiar with analog IC design flow 3.Familiar with Hspice or Spectre

待遇面議 員工600人
6~10人應徵

3/27 類比/資深類比IC設計工程師(台北/新竹)

  • 新竹縣竹北市
  • 3年以上
  • 碩士

1. 類比數位轉換器,數位類比轉換器(ADC/DAC), 2. Mixed-Signal & Analog Circuits (Switched-Capacitor Circuit, Bandgap, etc), 3. Analog-Front-End (AFE), Sensors, and Power Related IC (LDO, PoR, DC-DC, Bulk, Boost Converters). 4. 鎖相迴路設計、全數位式鎖相迴路設計、SerDes 5. Clocking related:PLL, DLL, CDR, TDC

待遇面議 員工300人
11~30人應徵

3/26 【台灣高價股高速介面 IC 大廠】Analog Design Engineer (SerDes)

  • 新北市新店區
  • 1年以上
  • 碩士

What We Are Looking For? - Knowledge of high-speed serial link technology. - Familiar with SerDes PHY (USB, PCIE Express, SATA and Thunderbolt) and building block (DFE, CTLE, CDR, PLL and FFE transmitter). - Experience in design and simulation high speed transceiver is a plus. - The background will be CDR and SERDES related. Basic Qualification - MSEE is required with 1+ year experience in analog design. __

待遇面議
0~5人應徵
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