4/26 SoC Physical Design Engineer (內湖)
- 英屬開曼群島商世芯股份有限公司台灣分公司
- IC設計相關業
- 台北市內湖區
- 1年以上
- 大學
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.