4/23 IC佈局(資深)工程師(台北)
- 博發電子股份有限公司
- IC設計相關業
- 台北市南港區
- 經歷不拘
- 高中
1. 類比IC佈局(Layout)經驗，做過BCD Prcoess尤佳 2. 需要負責全晶片整合佈局和DRC/LVS之驗證
4/23 【2024研發替代役/預聘｜校園徵才】RD Team_Analog Layout Engineer_類比IC佈局工程師 (台北)
- MPS_芯源系統有限公司
- IC設計相關業
- 新北市汐止區
- 經歷不拘
- 大學
Job Summary: Layout Engineer will work directly and indirectly with Design / CAD / Layout Manager in development of Mixed-Signal and Analog Integrated Circuits. Individual will perform job professionally and independently. The following are the requirements for this job function. Essential Functions: • Layout Schedule Estimation • Device Placement on block level according to matching requirements • Block implementations on Top Level • Signal matching / sensitive nets shielding technique • Pad / ESD rule and routing / connection • Database DRC & LVS verifications • Chip Tapeout in accordance with company's Tapeout Procedure • Positive Attitude Qualifications: • Layout experience in Analog and/or Mixed-Signal Circuit Design • Ability to do chip plan, estimate die size and project schedule • Ability to resolve DRC & LVS data verification and tape out chip independently • Familiarity with fundamentals of analog processes • Experience with Cadence and/or VIRTUOSO tools preferable
4/23 RF IC designer/manager
- 上緯科技電子股份有限公司
- 其他電子零組件相關業
- 新北市中和區
- 3年以上
- 碩士
1. Design RF IC in WiFi and IOT applications including SW/LNA/SAW/MEMS filter/Filter...etc. 2. Design of circuit link budget, topology and novel scheme development. 3. Optimization with process, device and system. 4. Measurement and optimization, bring to product launch
待遇面議
距捷運中原站約230公尺
4/23 【2024預聘｜校園徵才】RD Team_CAD Engineer_CAD 工程師 (台北)
- MPS_芯源系統有限公司
- IC設計相關業
- 新北市汐止區
- 經歷不拘
- 碩士
Job Summary: As an IC CAD engineer, you will collaborate closely with the design team to develop & maintain software/script solutions that enhance their workflow. This role involves operating within a multinational setting and participating in collaborative projects that demand cross-team coordination. Your responsibilities will encompass gathering requirements from these teams, devising a comprehensive plan, prototyping in a variety of programming languages, implementing an agile approach for ongoing project enhancements, and ultimately delivering a product aimed at enhancing overall team productivity. If you have a solid software background and decent knowledge on IC design, this is the job for you. Essential Functions: • Development of scripts for IC design automation. • Development of a continuous integration plus continuous delivery environment applied to IC design. • Data collection & visualization for design activities. • Document processes and flows. Qualifications: • Bachelor's degree in Electrical Engineering or Computer Science (MSEE or dual degree is preferable). • Fundamental grasp of Integrated Circuit design, encompassing Analog, Digital, or both. • Proficiency in Linux and basic Shell commands. • Proficiency in Python with main-stream packages / frameworks, such as Flask, Pandas, etc. • Elementary familiarity with web technologies, including JavaScript, Node, HTML, and CSS. • Capable of creating database schemas that accurately represent and facilitate business processes • Skillful in unit testing and debugging. • Experience with QT or PyQT • Competence in both SQL and NoSQL databases. • Proficiency with version control tools like SVN and Git. • Exposure to continuous integration, build tools (e.g., Jenkins, Ansible), and scripting.
4/23 【強固連結研究部】PCB佈線工程師
- 攸泰科技股份有限公司
- 電腦軟體服務業
- 台北市內湖區
- 經歷不拘
- 專科
●工作內容 1.具備電子電路相關概念，進行PCB Layout工作 2.熟悉Allegro/PADS Logic/CAM350/Orcad操作 ●工作流程 從PCB library零件建立，PCB Layout到 Gerber out *此工作非常適合熟悉或學習 Layout 作業* *非常適合擅於處理 PCB 板廠或PC板製程相關工作* *非常適合獨立執行作業與跨部門溝通之人才*
待遇面議
員工400人
4/23 Substrate Layout Engineer
- 美商集成全球科技股份有限公司
- IC設計相關業
- 新北市新店區
- 3年以上
- 專科
1. IC package substrate design and layout 1.1. Package type includes flip-chip and wirebond. Single die design and multi-die design 1.2. Substrate layer count from 2 layers to 20+ layers. Preferred experience is at least 4 layers (1-2-1) 1.3. High-speed (DDR, SerDes, PCIe...) signal routing optimization 1.4. Good knowledge in substrate layout design rules and package assembly design rules 2. Chip-Package-PCB co-design 2.1. Review die bump assignment and BGA ball assignment to provide suggestions to optimize the design
4/23 RD Team_Mixed-Signal Digital Design Engineer_混合訊號工程師 (台北/新竹)
- MPS_芯源系統有限公司
- IC設計相關業
- 新北市汐止區
- 3年以上
- 碩士
• A Mixed-Signal Digital Design Engineer assists on the Analog Design and Analog-Digital interface definition, design, validation, verification and integration of mixed-signal ICs utilizing leading edge technologies with industry standard ASIC tools. Products to be designed/verified may include power management, signal management and mixed signal functions. • MPS products include: switching regulators, sensors, motor control, display drivers, audio amplifiers and power management ICs for fast-growing portable and non-portable markets such as notebooks, cell phones, telecom, digital camera, automobile and network equipment.
4/22 ic佈局工程師
- 振生半導體股份有限公司
- 半導體製造業
- 台北市大安區
- 經歷不拘
- 學歷不拘
振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 工作內容： • 負責IC版圖的自動佈局佈線、優化和驗證。 • 負責簡單電路的設計和模擬。 • 負責部分全定製版圖的設計和驗證。 • 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。 我們期望您具備的條件： • 大學以上；電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子相關科系畢業為主。 • 具相關工作經驗者為佳。 • 良好的團隊合作和溝通能力。 相關報導： 數位時代：陽明交大出身的Jmem Tek的硬體資安技術有何特別？ https://meet.bnext.com.tw/articles/view/50065 DIGITIMES Asia報導：Chip startup JMEM TEK safeguards data security with hardware-software solution https://www.digitimes.com/news/a20221223VL202.html
4/22 台北｜ECAD應用工程師 (股票代號:3570)
- 大塚資訊科技股份有限公司
- 電腦系統整合服務業
- 新北市板橋區
- 5年以上
- 專科
大塚是一家充滿活力、快速成長的公司，歡迎在這裡找到屬於自己的舞台！ ●2008年10月股票掛牌上櫃 (股票代號3570) ●連續四年營收超越10億元 ●薪資水平在上櫃公司同業中名列前五名 ●擁有最完整的技術能量，每年客戶群超過2000家以上 ●是台灣產業涵蓋最廣的繪圖軟體解決方案代理商 ⭕ 工作內容 1. 熟悉電子硬體設計軟體，具電子產品開發經驗。 2. 提供客戶硬體設計與問題分析必要的技術支援。 3. 協助業務團隊推廣公司產品。 4. 具備良好溝通協調能力，主動積極，能獨立作業。 5. 配合專案執行，提供行銷建議、整理並製作技術文件。 ⭕ 需求條件 1. 具PCB Layout實務設計經驗5年以上 2. 熟悉PADS、PADS ROUTER、PADS LOGIC、Mentor產品軟體操作與應用 具備ORCAD、CAM350、ALLEGRO 尤佳 ⭕ 其他資訊 1. 薪資福利：依學、經歷面議核薪。 2. 上班時間：固定日班08:30-17:30 (含午休時間，彈性上下班30分)。 3. 依據公司經營狀況發放季獎金、年中分紅、年終獎金及員工酬勞等。
4/22 IC Layout 佈局工程師--台北
- 矽拓科技股份有限公司
- 半導體製造業
- 台北市內湖區
- 經歷不拘
- 專科
1.對類比IC Layout 有興趣者, 英文或日文中等, 歡迎非本科系 2.無工作經驗可 3.相關科系.有英文或日文相關證照者佳
4/22 IC實體設計(APR)工程師-新店
- 慧榮科技股份有限公司_SMI
- IC設計相關業
- 新北市新店區
- 3年以上
- 大學
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.
4/22 Layout工程師
- 億光電子工業股份有限公司
- 光電產業
- 新北市樹林區
- 經歷不拘
- 大學
1.Layuot設計，PCB發包製作，SMT/DIP發包製作。 2.研究製作PCB產品相關分析與報告。 3.協助技術文件編寫。 Job Description 1.Layout design, PCB outsourcing and production, SMT/DIP outsourcing and production. 2.Research and create analyses and reports related to PCB product manufacturing. 3.Assist in the preparation of technical documents.
4/22 Layout 工程師-RJ00
- 映泰股份有限公司
- 電腦及其週邊設備製造業
- 新北市新店區
- 2年以上
- 專科
1. 負責 PC主機板/ IPC 主機板/ 平板主機板/ NoteBook主機板之 PCB Layout (使用 Cadance Allegro Placement,Routing,modify,Gerber out)設計 2. 對於 PCB 板廠製程及工廠SMT製程需有基本概念 3. 能夠完成Layout作業及團隊合作跟善於與人員做溝通協調
4/22 資深IC實體設計工程師(APR)-新店
- 慧榮科技股份有限公司_SMI
- IC設計相關業
- 新北市新店區
- 5年以上
- 大學
Physical design, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, DRC/LVS to tapeout.
4/22 IC佈局工程師IC Layout Engineer/學生實習 Intern
- 宏芯科技股份有限公司
- IC設計相關業
- 新北市中和區
- 經歷不拘
- 碩士
1、Experienced in mixed-signal MOS transistor level layout design. 2、Can perform low-noise and less parasitic analog layout design. 3、Knowledge of Analog and Digital layout integration is a plus. 4、Can perform LVS, DRC, and ERC checks. 5、Can perform top-level floor planning, which includes efficient block arrangement, proper placement of I/Os, and considering ESD path. 6、Understands the effect of layout parasitic especially on sensitive blocks such as VCO and high-speed circuits. 7、Proficiency on commonly used EDA tools for layout design such as Cadence Virtuoso and Laker
待遇面議
員工80人
4/22 1E100-類比IC設計工程師
- 驊訊電子企業股份有限公司
- IC設計相關業
- 台北市大安區
- 5年以上
- 碩士
1. PLL/CDR and audio codec (Signa-Delta ADC/DAC) design. 2. Analog power circuits (LDO/DC-DC converter/ charge pump) design. 3. USB PHY TX/RX design. 4. ESD/latch up/IO design. 5. Analog circuits simulation, chip integration and debug.
4/22 Analog Layout Engineer
- 安科諾科技有限公司
- 其他半導體相關業
- 新北市新店區
- 5年以上
- 碩士
As a member of the Analog RF team you will be responsible to deliver fully-verified, clean layout, this includes the following: 1. Designing complex layout for mixed signal, analog and RF circuits in deep sub-micron CMOS technologies. 2. Reviewing and analyzing floorplans and complex circuits with circuit design engineers. 3. Working with circuit design team to plan/schedule work and negotiate any necessary layout tradeoffs as needed. 4. Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout. 5. Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area and power requirements.
4/22 G240003-Physical Design Engineer/ Technical Manager
- 創意電子股份有限公司
- IC設計相關業
- 台北市內湖區
- 2年以上
- 碩士
※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. Have experiences in 65/40/28nm IC design experiences will be plus.
4/22 Layout工程師
- 沅聖科技股份有限公司
- 其他電子零組件相關業
- 新北市中和區
- 3年以上
- 專科
1. 依照硬體設計，完成產品的placement 和PCB佈線(熟多層板,盲埋孔layout) 2. 電子零件庫的建立與維護 3. 熟電子電路基本原理，能依據Design Guideline與設計者討論 4. 協助RD回覆PCB製作之相關工程問題 5. Layout Rule的規劃與制定
待遇面議
員工150人