●工作內容 1.具備電子電路相關概念，進行PCB Layout工作 2.熟悉Allegro/PADS Logic/CAM350/Orcad操作 ●工作流程 從PCB library零件建立，PCB Layout到 Gerber out *此工作非常適合熟悉或學習 Layout 作業* *非常適合擅於處理 PCB 板廠或PC板製程相關工作* *非常適合獨立執行作業與跨部門溝通之人才*
振生半導體股份有限公司 (Jmem tek) 專注於半導體相關矽智財，提供設計服務與硬體資安專利，保護硬體資訊安全。如果您希望參與一個充滿潛力和創造力的環境，歡迎您加入我們的團隊。 工作內容： • 負責IC版圖的自動佈局佈線、優化和驗證。 • 負責簡單電路的設計和模擬。 • 負責部分全定製版圖的設計和驗證。 • 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。 我們期望您具備的條件： • 大學以上；電機、電機與控制、資訊科學、自動控制、通訊工程、電信、資訊工程、電子相關科系畢業為主。 • 具相關工作經驗者為佳。 • 良好的團隊合作和溝通能力。 相關報導： 數位時代：陽明交大出身的Jmem Tek的硬體資安技術有何特別？ https://meet.bnext.com.tw/articles/view/50065 DIGITIMES Asia報導：Chip startup JMEM TEK safeguards data security with hardware-software solution https://www.digitimes.com/news/a20221223VL202.html
1. 類比IC佈局(Layout)經驗，做過BCD Prcoess尤佳 2. 需要負責全晶片整合佈局和DRC/LVS之驗證
1.對類比IC Layout 有興趣者, 英文或日文中等, 歡迎非本科系 2.無工作經驗可 3.相關科系.有英文或日文相關證照者佳
1. PLL/CDR and audio codec (Signa-Delta ADC/DAC) design. 2. Analog power circuits (LDO/DC-DC converter/ charge pump) design. 3. USB PHY TX/RX design. 4. ESD/latch up/IO design. 5. Analog circuits simulation, chip integration and debug.
※ Job Contents: 1. Perform Netlist-to-GDS design flow, including floorplanning, placement, timing optimization, clock tree synthesis and routing. 2. Support STA timing analysis and fixing 3. Perform physical verification, including DRC, LVS, IR drop and DFM analysis. ※ Requirements: 1. Familiar with Cadence Innovus or Synopsys ICC2/Fusion Compiler. 2. TOEIC 730~855 is preferred. 3. Have experiences in 65/40/28nm IC design experiences will be plus.
1. In charge of implementing digital circuits for mixed-signal design (from gate level netlist to GDS) 2. Performing daily tasks including floor-plan, CTS, PnR, STA, Power budget, IR-drop / EM / Cross-talking analysis and sign-off. 3. Estimation of efforts and schedules for assigned project. 4. Close cooperation and interaction with other design teams in different company sites.
1. UPS及PV-INVERTER 產品線路圖繪製和PCB佈局走線繪製規劃． 2. 配合硬體和機構前期的layout placement擺放評估． 3. 研發或生產中PCB存在的問題進行分析，改善．
1. Perform gate level netlist to GDS design independently including and not limit to floor planning, place&route, clock tree synthesis, timing sign off and physical verification. 2. For DFT engineers, need to able to implement scan chain, atpg, mbist, jtag, IP test logic into netlist. 3. Perform design IP implementation, IR drop analysis, DFT, STA and foundry merge. 4. Work with manager to achieve assigned tape out target.
1.根據設計工程師的要求進行IC佈局設計和驗證 2.熟悉代工廠所提供的design kit，佈局規則和驗證工具 3.與設計工程師充分溝通，確保滿足設計工程師對佈局的要求 4.根據不同IC代工廠的要求進行tapeout和maskview 5.高速介面IC layout及低功耗IC佈局設計 IC佈局工程師在現今高科技產業中扮演著至關重要的角色，他們負責設計、佈局、驗證和優化積體電路的電氣和物理佈局，確保產品滿足高品質、高性能和低功耗等要求。這是一個快速發展的職業領域，擁有豐富的晉升空間和發展前景。 如果您擁有上述要求並對此職位感興趣，請即刻申請加入我們的團隊！
1. 收集及諮詢客戶有關行程、交通工具、旅館住宿及花費成本等資料，安排旅遊、預訂旅館並接受付款。 2. 必要時亦協助推銷或籌組旅行團，包括團體或個人。 3. 協助顧客取得必要證件及旅遊文件。 4. 安排個人旅遊或旅行團所需之領隊或導遊人選
1. Responsible for ASIC physical implementation by using automatic place and route tools. The P&R processes including floorplanning, power plan synthesis and analysis, physical timing optimization, clock tree synthesis, routing, and post-routing optimizations. 2. Responsible for physical verification including DRC, LVS and ESD checking.
負責先進製程實體設計(APR in 5nm/7nm), 包含physical synthesis(DCG), floorplan, powerplan, placement, CTS, routing, timing fixing and DRC/LVS, . . ., etc. 1. APR hierarchical design flow. 2. Physical design project execution. 3. Responsible for physical verification including DRC, LVS and ESD checking. 4. Static timing analysis by using Synopsys PrimeTime. 5. Work Assignments. 6. Interdepartmental communication and collaboration.
【工作職責 (Responsibilities)】： ★ Netlist-to-GDS design flow. including power plan, floorplan, placement, timing optimization, clock tree synthesis and routing ★ STA timing analysis and fixing ★ Physical verification, including DRC, LVS, IR drop and DFM analysis. ★ Physical design flow development and automation 【符合條件 (Qualifications)】： 必須條件 (Minimum Qualifications)： ★ 電機、資訊相關科系，學士或碩士畢業 ★ 具有獨立思考的能力，並習慣與團隊合作解決問題 ★ 高度的學習動機、願意投入精力分析和解決問題 優秀條件 (Preferred Qualifications)： ★ 具有IC相關 tape out經驗 ★ 熟悉Tcl, Python語言
1. Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2. Responsible for Physical Design flow research, development and automation.
Front-End RTL Coding & Verification (I/O peripherals and MCU) Altera&Xilinx FPGA Application development C-Coding
1.Responsible for ASIC Backend / Physical Implementation, including floorplan, power plan, physical synthesis, clock tree synthesis, routing, si, DFM, DRC/LVS in both hierarchical and low power designs. 2.Responsible for Physical Design flow research, development and automation.
1.5年以上IC設計或IC設計服務CAD相關經驗 2.熟Synopsys or Cadence RTL to Gdsii相關軟體(Synopsys尤佳) 3.熟Perl, TCL/TK, Shell相關程式 4.EDA tool evaluation and benchmark 5.Support Sales/Marketing
1.三年以上Analog IC layout 經驗 2.熟laker、Virtuoso 等相關Edit Tools 3.熟Calibre、Dracula等layout Verification
candidate to (Jab need ) : Has on-hands experience on SMT 8 test program debug Our preference is to find a Mandarin+English speaking candidate. We need this candidate to perform backend test tasks which come under "post silcon process". Experience: > 3 years will be the best range, Taiwan national, Male or female. -> Suggest experience > 3 years Skill Knowledge: Silicon ATE 93K SMT 8 test debug and HW debug experience.