4/26 VIS220181-Standard Cell Designer(新竹廠)
- 世界先進積體電路股份有限公司
- 半導體製造業
- 新竹市
- 經歷不拘
- 碩士
1. Standard cell library develop & maintain. 2. Cadence's & Synopsys's APR flow develop 3. Digital design flow consults
1. Standard cell library develop & maintain. 2. Cadence's & Synopsys's APR flow develop 3. Digital design flow consults
1.科系:碩士以上,理工相關系所(電子/電機系所,資訊工程所畢業尤佳)。 2.班制:常日班。 3.工作內容: (1)Responsible for SRAM Macro / SRAM Compiler Design. (2)SRAM Circuit Development; Verification and Maintenance 4.說明: (1)請於履歷表中註明論文主題(方向)及所學專長。 (2)請檢附學士(含)以上之成績單。
1.需求科系:碩士以上,(微)電子、電機、電物、資訊等相關系所畢。 2.班制:常日班。 3.工作內容: (1)製程開發平台之DRC/LVS/LPE開發維護 (2)新EDA應用流程及軟體(PERC/QRC/PVS)之程式開發維護 (3)協助客戶解決產品開發設計階段實體驗證以及驗證諮詢服務 4.說明: (1)請於履歷表中註明論文主題(方向)及所學專長。 (2)請檢附學士(含)以上之成績單。
1. 負責GPIO 及客製化IO 開發與Test chip tape out 及驗證工作。 2. 協助客戶進行 IO 規格確認、使用與IP Qualification 品質項目服務。 3. 支援與協調GPIO設計、測試與電性分析等相關議題。
Job Responsibilities: You will be working with global teams in Argentina, Singapore, the U.S., and throughout Europe. You’ll receive a schematic from an Analog IC Designer. You will then take that schematic and use a CAD tool to graphically design the layers of that schematic. Then, you run simulations and verifications on the design using Cadence Virtuoso, refine and debug as needed in concert with the designer, and both of you keep iterating the design until it meets the desired specifications. Each project can last from a couple of months to a year and a half. You will likely work on just one project in that time but may be asked to switch to something else if priorities change. Your flexibility is appreciated. You’ll meet every few days with the designer you’re paired with to share information and work together. No circuits get built or tested here without you both, so your partnership and teamwork are extremely valuable to Marvell. You’ll also have routine meetings with your technical mentor when you have questions, as well as the layout team and the project team where you may have to speak to the entire group and update them about your progress. You may have to present a particular issue or solution you’ve encountered. We are developing brand new cutting-edge technologies here, so we learn new things frequently and share them with our colleagues.
擴大規模,大量徵才 1.專業Full Custom IC layout 2.對IC Layout 有興趣者, 須具有清晰之 邏輯觀念
1.IC fully layout 2.類比 IC Layout 經驗者佳或具APR經驗者。 3.具Tape out 量產經驗,能獨立處理Whole Chip者優先考慮 4.熟悉layout tool或verification tool等工具軟體的使用 5.懂 Latch-up/ESD/Cross-section 者優先考慮
C佈局工程師 1. 負責IC版圖的自動佈局佈線、優化和驗證。 2. 負責簡單電路的設計和仿真。 3. 負責部分全定製版圖的設計和驗證。 4. 負責CMOS Sensor規格訂定,系統驗證及Demo Board設計。 5. 確保IC佈局符合Circuit Designer設計需求及產品、製程、電氣的規範。
• Co-work with package design team to complete a substrate layout that will meet the design objectives for performance, cost and quality. • Co-work with SOC team to complete Bump floorplan and RDL routing. • Power mesh/power density flow development and related flow development and enhancement. • Provide power plan result for PR team. • Chip IR signoff : provide the result and solution to APR & package team • Chip level PEM/SEM simulation and fixing plan providing. • SIR/DIR/PEM/SEM result data review and verification. • Familiar with Voltus / Redhawk experience is required.
1.Fully custom IC layout for analog 2.Channel or whole chip integration 3.Responsible for layout design,layout verificaion and tapeout.
1. APR physical design: floorplan, power plan,physical synthesis, clock tree, routing, DRC/LVS to tapeout 2. APR methodology Development & Automation
1. APR physical design, including floorplan, power plan, clock tree, routing, timing closure. 2. STA , IR Analysis, DRC/LVS to tapeout.
1. 負責產品之佈局、DRC、LVS, 並產生供光罩製作之data base。 2. 具IC佈局相關工作經驗,須了解製程與ESD、Latch up。 3. 熟悉 Laker, Calibre.
(1)Analog and Digital IC Layout或具APR經驗者。 (2)熟悉Laker Tool與Calibre verificaiton Tool等工具軟體使用。
1協助處理無刷/有刷電路板製程優化 2.協助排除生產狀況異常 3.參與產線優化規劃 4. 參與電控課相關作業及達標準管理 5.歡迎電子相關科系應屆畢業生 6.無經驗可
1. Mixed-mode Layout 相關經驗或具APR經驗者 2. 熟悉layout相關軟體的使用(Virtuoso, Laker, Calibre) 3. 有解決 Latch-up/ESD/Cross-section的經驗
1. 有wholechip經驗,能獨立且佈局符合circuit designer設計需求 2.Layout tool 操作熟悉( Laker OA,Laker3,Calibre DRC/LVS check) 3.有TSMC,UMC,HHGrace相關製程經驗 4.有高壓或Analog IC layout經驗