1. Calibre PERC/LVS/DRC command file維護及in-house command file撰寫 2. 驗證自動化流程開發(Shell/TCL/Ptyhon/Perl) 3. Physical Design/Layout 自動化程式及QC程式開發 (Shell、TCL、Python、Html/CSS、Java) 4.具Innovus/ICC2使用經驗，熟Cadence DBA語法尤佳 5.具 12/7/5nm Physical design experiences is a plus.
1.Familiar with block-level/high-speed IP physical imeplementation by Innovus/ICC2 2.Familiar with Laker, Virtuso, Calibre for layout verification 3.Familiar with STA for timing closure. 4.Programming skill for flow automation is plus
本職務之工作主要是協助實體設計部門，做whole chip的layout verification，其中包括DRC/LVS/PERC等驗證工作，並協助部門做自動化程式的撰寫及流程的開發，熟悉tcl/Python者尤佳。
High-Speed Circuit (TX/RX, PLL, CDR)，ESD I/O Pad及Power IC ...等的佈局實現
1. Familiar with APR hierarchical flow 2. Familiar with Innovus, Tempus/PrimeTime, Tweaker, Laker/Virtuso, Calibre for layout verification 3. Familiar with STA for timing closure 4. With 12nm process(or blow) tapeout experience is plus 5.Programming skill for flow automation is plus
呃拍謝，搜尋結果好像很少
可以嘗試調整條件、或看看你專屬的推薦工作
• Work on 22nm~6nm design implementation, methodology, and sign-off • Perform floorplan, power plan, place and route, timing closure, ECO, early IR signoff, and early physical verification • Manage schedule, resolve design and flow issues, drive methodologies and execution • Requirement： - Hands on whole chip APR physical design from netlist to DRC/LVS tapeout - Familiar with Cadence Innovus & Synopsys ICC/ICC2 experience is required
擔任CAD (Physical Verification Design) 工作內容: 1.負責Command file撰寫與Maintain 2.Physical PG Sign-off Check 3.流程與程式開發 4. 需求條件: 4-1 工作經歷 : 2年以上，有先進製程(FinFET)經驗尤佳 4-2 擅長工具 : Calibre 、 ICV、TCL 4-3 工作技能 : DRC/LVS Command File撰寫 & 程式開發 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠
Position Description: • Development of efficient PERC decks for Cadence Physical Verification tool with leading foundry processes and design kits. • Cooperate with foundry partners on various outsourcing projects for verification flow. • Communicate with R&D to capture customer needs and requirement spec. • Work closely with early adoption customers to track and resolve product issues. • Be a team-player to co-work with R&D/PE on problem resolving and the solution delivery. Position Requirements: • MS in Electrical Engineering (EE), Computer Science (CS), Physics or related area (or equivalent) and at least 3 years of experience with Physical Design/Verification tool support/development. • Excellent script programming skills on TCL and Perl are required. • Good communication skills in English. • Good problem-solving skills. • In-depth knowledge on either ESD, ERC, PERC, gate level netlist, and circuit structure is preferred. • Knowledge of software development cycle is preferred.
1. ARM CPU/GPU, DSP front end implementation including high speed RTL synthesis and DFT. 2. Front end verification including logic equivalence check, constraint quality check, static timing analysis and ATPG. 3. Requirement: 3-1. Familiar with front end implementation design flow 3-2. Familiar with Synopsys synthesis and Mentor DFT/ATPG tools 3-3. Expertise in CPU/GPU/DSP front end implementation 3-4. Good communication skill is plus 【共創A+聯詠】 穩健踏實、專家精神、創造優勢 驅動科技、開發創新、引領未來 邀請優秀人才，共創A+聯詠 上班地點: 「台北」或「竹北」
1.Support and maintain EDA tools and flows used in the digital IC implementation. 2.Design and develop methodologies, automation scripts, and design flow. 3.Manage version control system (Git/SVN), issue tracking system, and CI/CD flow. [Requirement] 1.Python/Perl/TCL/Shell programming skills. 2.Familiar with EDA tools for IC design flow. 3.Basic knowledge of Verilog or SystemVerilog HDL.